Analog Devices ADSP-SC58 Series Hardware Reference Manual page 729

To minimize this delay, the wrap feature can be used where the memory subsystem provides the address of the criti-
cal word.
• For MDMA reads, the number of read data bytes (N) is always equal to 4 bytes. The MDMA read does not
depend on the cache setting. For MDMA reads, limit the DMA_CFG.MSIZE field to 1, 2 or 4 bytes. The
address provided by the memory subsystem master to the SPI hardware is always 4 byte-aligned.
Memory-Mapped High-Performance Features
In addition to automating the SPI memory read accesses, the memory-mapped hardware also provides some features
to improve SPI memory fetches and increase the system performance. The following sections describe these features.
Merged Read Accesses
It is common for the memory subsystem to fetch two or more cache lines from consecutive addresses (the address
sequencing is linear without any jumps). To take advantage of this situation, the SPI memory-mapped hardware
provides a feature called merging. Enable merging by setting the SPI_MMRDH.MERGE bit.
When enabled, the hardware compares the address of an incoming read request to the address of a request the SPI
memory is actively servicing. It can decide to merge two accesses when the address for the second access is incremen-
tal. For example, if the first address of a 32-byte cache line fetch is 0x0000_0000 and the second fetch is to address
0x0000_0020, then these two accesses can be merged. Merging increases efficiency and overall fetch bandwidth by
eliminating the read header for those accesses which only require continuation of the SPI clock.
Wrap Around Accesses
Many SPI flash memory devices support wrapping which is used to enhance critical word fetching of cache lines. In
this mode, the SPI device automatically wraps the read address to the base of a cache line once the end of the cache
line is reached.
Wrap around accesses are enabled by setting the SPI_MMRDH.WRAP bit.
Some flash devices require programs to send a Set Wrap command to place the device in wrap mode. Other flash
devices provide a configuration register which must be programmed to set the flash in wrap mode. Since the SPI
memory-mapped hardware does not support any write operations to flash, perform this step in non-memory-map-
ped mode (SPI_CTL.MMSE=0) by accessing the SPI registers.
Table 16-9: Wrap Modes
Cache Line Size Wrap Mode
4-byte Not applicable
8-byte 8 byte wrapping
16-byte 16 byte wrapping
32-byte 32 byte wrapping
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Comments
Usually flash does not support 4-byte wrapping.
Read data wraps within an aligned 8-byte boundary starting from the
specified address.
Read data wraps within an aligned 16-byte boundary starting from the
specified address.
Read data wraps within an aligned 32-byte boundary starting from the
specified address.
Memory-Mapped Mode (SPI2 only)
16–23