Table of Contents
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Single Rate Processing .............................................................................................................................. 51–8
Single Iteration...................................................................................................................................... 51–8
Floating-point Multi-Iteration............................................................................................................... 51–8
Window Processing ................................................................................................................................. 51–8
Multi-Rate Processing .............................................................................................................................. 51–9
Decimation............................................................................................................................................... 51–9
Interpolation ............................................................................................................................................ 51–9
Channel Processing ................................................................................................................................ 51–10
Floating-Point Data Format.................................................................................................................... 51–11
Fixed-Point Data Format ........................................................................................................................ 51–11
Data Transfer............................................................................................................................................. 51–12
Chain Assignment .................................................................................................................................. 51–12
DMA Access ........................................................................................................................................... 51–13
Accelerator TCB ..................................................................................................................................... 51–13
Chain Pointer DMA ............................................................................................................................... 51–13
Programming Model.................................................................................................................................. 51–14
Single Channel Processing ...................................................................................................................... 51–14
Multichannel Processing......................................................................................................................... 51–14
Dynamic Coefficient Processing Notes ................................................................................................... 51–15
Debug Mode .......................................................................................................................................... 51–16
Write to Local Memory ....................................................................................................................... 51–16
Read from Local Memory.................................................................................................................... 51–16
Single-Step Mode ................................................................................................................................... 51–16
FIR Programming Example .................................................................................................................... 51–16
Computing FIR Output, Tap Length Greater than 4096........................................................................ 51–17
Debug Features .......................................................................................................................................... 51–18
Local Memory Access ............................................................................................................................. 51–19
Single-Step Mode ................................................................................................................................... 51–19
Emulation Considerations ...................................................................................................................... 51–19
Interrupts................................................................................................................................................... 51–19
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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Table of Contents
