ADSP-SC58x PORT Register Descriptions
Table 14-24: PORT_POL_CLR Register Fields (Continued)
Bit No.
(Access)
12
PX12
(R/W1C)
11
PX11
(R/W1C)
10
PX10
(R/W1C)
9
PX9
(R/W1C)
8
PX8
(R/W1C)
7
PX7
(R/W1C)
6
PX6
(R/W1C)
5
PX5
(R/W1C)
4
PX4
(R/W1C)
3
PX3
(R/W1C)
14–66
Bit Name
Port x Bit 12 Polarity Invert Clear.
Port x Bit 11 Polarity Invert Clear.
Port x Bit 10 Polarity Invert Clear.
Port x Bit 9 Polarity Invert Clear.
Port x Bit 8 Polarity Invert Clear.
Port x Bit 7 Polarity Invert Clear.
Port x Bit 6 Polarity Invert Clear.
Port x Bit 5 Polarity Invert Clear.
Port x Bit 4 Polarity Invert Clear.
Port x Bit 3 Polarity Invert Clear.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.
0 No Effect
1 Clear Bit. Set to disable GPIO pin polarity invert.