Analog Devices ADSP-SC58 Series Hardware Reference Manual page 900

Table 18-49: EPPI_CTL Register Fields (Continued)
Bit No.
(Access)
6 FLDSEL
(R/W)
5:4 FSCFG
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Field Select/Trigger.
The EPPI_CTL.FLDSEL bits configure the EPPI field and trigger selection. These
are valid for GP modes (EPPI_CTL.XFRTYPE =0x3) and ITU656 active video
mode (EPPI_CTL.XFRTYPE cleared).
Frame Sync Configuration.
The EPPI_CTL.FSCFG bits configure the EPPI frame syncs. These are valid only
for GP modes (EPPI_CTL.XFRTYPE =0x3). The output of the frames syncs also
depends on whether the EPPI transfer direction is transmit and the EPPI is in ITU
output mode (EPPI_CTL.BLANKGEN is set).
ADSP-SC58x EPPI Register Descriptions
Description/Enumeration
0 Field Mode 0. Read field 1 (for ITU656 active video
mode). Set internal trigger (for GP RX mode). FS3 is
toggled on FS2 assertion followed by FS1 assertion
(when the EPPI_CTL.FSCFG bit selects sync mode 3
and the EPPI_CTL.IFSGEN bit selects internal frame
sync).
1 Field Mode 1 Read field 1 and field 2 (ITU656 active
video mode). Set external trigger (GP RX mode). FS3 is
toggled on FS2 assertion (when the
EPPI_CTL.FSCFG bit selects sync mode 3 and the
EPPI_CTL.IFSGEN bit selects internal frame sync).
0 Sync Mode 0. FS0 driven in GP mode. FS0 not driven
in ITU output mode.
1 Sync Mode 1. FS1 driven in GP mode. HSYNC driven
on FS1 in ITU output mode.
2 Sync Mode 2. FS2 driven in GP mode. HSYNC driven
on FS1 and VSYNC driven on FS1 in ITU output
mode.
3 Sync Mode 3. FS3 driven in GP mode. HSYNC driven
on FS1, VSYNC driven on FS2, and FIELD driven on
FS3 in ITU output mode.
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