Analog Devices ADSP-SC58 Series Hardware Reference Manual page 723

SPI MEMORY MAPPED READ
TRANSFER INITIATED
SEND READ ADDRESS
SPI FLASH MEMORY DRIVES THE DATA OUT. SPI HARDWARE READS THE DATA.
Figure 16-13: SPI Memory-Mapped Register Operations Flow
Memory-Mapped Architectural Concepts
In memory-mapped mode, the SPI accepts read requests through a dedicated on-chip slave interface. The SPI (if
ready) accepts these requests and begins the process of assembling the read header based on access attributes descri-
bed in both the SPI_MMRDH
pin turnaround period is timed and the receiver is enabled. The SPI continues clocking the SPI memory device until
all bytes are received.
The SPI memory-mapped hardware accommodates various memory devices with different read timing. The capabil-
ities include extra mode bits, flexible dummy period timing, and three-state control, as configured in the
SPI_MMRDH register.
The Memory-Mapped Protocol figure shows the protocol for the SPI controller in memory-mapped mode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
0
MMRDH. MMRDH.
CMDSKIP CMDPINS
0
SEND MMRDH.OPCODE
ON MOSI PIN
2
MMRDH. CTL.
1
ADRPINS MIOM
0
0
SEND READ ADDRESS
ON MOSI PIN
ON MOSI AND MISO PINS
INSERT THE DUMMY CYCLES AS SPECIFIED IN MMRDH.DMYSIZE
SEND THE MODE BITS AS
SPECIFIED IN MMRDH.MODE
PIN TURN-AROUND IN PREPARATION OF RECEIVE DATA
register and the internal bus request. After the read header transmission is complete, a
2
1 1
CTL.
MIOM
0
SEND MMRDH.OPCODE
ON MOSI AND MISO PINS
1
SEND READ ADDRESS
ON MOSI, MISO D2,
AND D3 PINS
THREE-STATE THE
I/O DATA PINS AS PER
MMRDH.TRIDMY SETTING
Memory-Mapped Mode (SPI2 only)
COMMAND
PHASE
SEND MMRDH.OPCODE
ON MOSI, MISO D2,
AND D3 PINS
ADDRESS
PHASE
DUMMY
PERIOD
PHASE
DATA
PHASE
A:
B:
C:
D:
16–17