Analog Devices ADSP-SC58 Series Hardware Reference Manual page 451

Table 10-21: DMC_MR Register Fields (Continued)
Bit No.
(Access)
6:4 CL
(R/W)
2 CL0
(R/W)
1:0 BLEN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
CAS Latency.
The DMC_MR.CL bit field selects latency from the assertion of a read/write signal to
the SDRAM until the first valid data on the output from the SDRAM in terms of
clock cycles. For more information about this operation, see the data sheet for the
SDRAM being used in your system.
The valid numbers for DDR2 and LPDDR are:
010 = Reserved
011 = 3
100 = 4 (DDR2 only)
101 = 5 (DDR2 only)
110 = 6 (DDR2 only)
For DDR3 only bit [2] DMC_MR.CL0 should be used along with bits [6:4]:
0010 = 5
0100 = 6
0110 = 7
1000 = 8
1010 = 9
1100 = 10
1110 = 11
0001 = 12
0011 = 13
0101 = 14
All other combinations are reserved.
CAS Latency 0.
The DMC_MR.CL0 bit is applicable for DDR3 only and is used in conjunction with
the DMC_MR.CL bits.
Burst Length.
The DMC_MR.BLEN bits select burst length for transfers. For more information about
this operation, see the data sheet for the SDRAM being used in your system. Note that
values other than those shown are not supported.
ADSP-SC58x DMC Register Descriptions
Description/Enumeration
0 8-Bit Burst Length - DDR3 only
2 4-Bit Burst Length -LPDDR/DDR2 only
3 8-Bit Burst Length - LPDDR/DDR2 only
10–45