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Configuring CGU Modes
a. To change the PLL frequency while the cores are idle, write to the
CGU_CTL.WFI bit =1.
b. To change the PLL frequency while the cores are active, write to the
CGU_CTL.WFI bit =0.
This sequence performs these actions:
1. Updates the corresponding CGU registers
2. Bypasses the PLL
3. Makes the PLL lock to the new values in the CGU_CTL.MSEL or CGU_CTL.DF fields
4. Changes the clock frequencies
5. Exits the PLL bypass with all clocks aligned
When exiting the PLL bypass state, a CGU event occurs.
The
register exits this sequence with the CGU_STAT.PLLEN bit =1, the CGU_STAT.PLOCK bit =1,
CGU_STAT
the CGU_STAT.PLLBP bit =0, and the CGU_STAT.CLKSALGN bit =0. Poll the CGU_STAT.PLOCK bit,
CGU_STAT.PLLBP bit, and CGU_STAT.CLKSALGN bit to discover when the PLL is locked and the clocks are
aligned.
Changing the frequency of the PLL is allowed while the PLL is bypassed. But, the new PLLCLK frequency is not
used until the PLL is no longer bypassed.
Changing the CCLKn or SYSCLK Frequency Without Modifying the PLLCLK Frequency
To change the clock frequencies, write new values to CGU_DIV.CSEL or CGU_DIV.SYSSEL bits. The frequen-
cy change occurs only when the PLL is not bypassed. Any time the CCLKn or SYSCLK clock frequencies are
changed, they exit the frequency change sequence aligned.
1. Read the
CGU_STAT
2. Write the desired CGU_DIV.CSEL, CGU_DIV.SYSSEL, and CGU_DIV.OSEL bit field values with the
CGU_DIV.UPDT bit = 1.
ADDITIONAL INFORMATION: This write updates the
frequencies, and aligns the clocks. When the clocks are aligned, a CGU event occurs.
The
register exits this sequence with the CGU_STAT.CLKSALGN bit =0. Poll the
CGU_STAT
CGU_STAT.CLKSALGN bit to discover when the clocks are aligned. Any write attempt to change the
CGU_DIV.S0SEL or CGU_DIV.S1SEL bit fields while CGU_STAT.CLKSALGN bit =1 (clocks alignment in
progress) triggers an MMR access bus error and the
Programming the SYSCLK frequency to a higher value than CCLKn also triggers an MMR access bus error and the
CGU_DIV
register is not modified.
3–10
register to verify that the CGU_STAT.CLKSALGN bit =0 (clocks aligned).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register, changes the SCLKn and SYSCLK
CGU_DIV
register is not modified.
CGU_DIV
CGU_CTL
register with the
register with the
CGU_CTL
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