Analog Devices ADSP-SC58 Series Hardware Reference Manual page 836

Transmit Address/Insert Pulse Register
The register and the
UART_TAIP
ferent effect than the UART_THR
In MDB mode, data written to the
UART_CTL.MOD bit set).
In UART mode, a write to
[6:0] x bit time. (There is additional inversion if the UART_CTL.TPOLC bit is set).
Bit time is defined by the
specified by the UART_CTL.STB and UART_CTL.STBH bits. This could be used for supporting line break com-
mand and inter-frame gap.
In IrDA mode, writes to
Accesses to the UART_TAIP
UART_STAT.THRE, UART_STAT.TEMT, and UART_STAT.TFI flags.
Figure 17-21: UART_TAIP Register Diagram
Table 17-20: UART_TAIP Register Fields
Bit No.
(Access)
7:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART_THR
register when
UART_TAIP
causes a pulse of value
UART_TAIP
UART_CLK register. The transmission of the pulse is followed by stop bit transmission as
is treated the same as writes to UART_THR.
UART_TAIP
register have the same affects as the
15 14 13
0 0 0
VALUE (R/W)
8-bit data
31 30 29
0 0 0
Bit Name
8-bit data.
register share the same physical register, but
UART_TAIP is written to in MDB and UART modes.
register is transmitted as an address frame (as with the
UART_TAIP
UART_THR
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x UART Register Descriptions
UART_TAIP
[7] for a duration of
register with respect to the
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0
has dif-
UART_TAIP
17–49