Analog Devices ADSP-SC58 Series Hardware Reference Manual page 683

ADSP-SC58x LP DMA Channel List
Table 15-5: ADSP-SC58x LP DMA Channel List
DMA ID
DMA30
DMA36
Block Diagram
The Link Port Block Diagram shows the block diagram of a link port.
Figure 15-1: Link Port Block Diagram
External Connections
As shown in the Link Port Pin Connections figure, a link port has eight data lines (LP_D0 – LP_D7), a clock line
(LP_CLK), and an acknowledge line (LP_ACK). A link port can act as either a transmitter or a receiver but not
both at the same time.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMA Channel Name
LP0_DMA
LP1_DMA
LDATx7-0
MUX
TRANSMIT SHIFT
REGISTER
Status
TRANSMIT FIFO
2-DEEP
DDE
PERIPHERAL BUS
LOCAL SCB ARBITER INTERFACE
SYSTEM SCB INTERFACE
LACKx
Transfer Direction
RECEIVE PACK
REGISTER
RECEIVE FIFO
Status
4-DEEP
DDE
LP Functional Description
Description
LP0 DMA Channel
LP1 DMA Channel
LCLKx
CONTROL AND
STATUS
15–3