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ADSP-SC58x L2CTL Register Descriptions
Write Priority Count Register
The
register stores the count value to be used for priority elevation for bus write channels. If a bus
L2CTL_WPCR
channel is not granted access from the bank arbiter, the channel waits for the programmed number of SYSCLK_0
cycles, before the request is elevated to a high priority request. If a priority count value is programmed as zero for a
channel, that channel does not raise the urgent priority request.
This is a read/write register, but a new value in the corresponding field must be written only when there are no
outstanding transactions on the corresponding bus write channel. A best practice is to program this register before
initiating an L2 access.
WPC1 (R/W)
Write Priority Count 1
Figure 9-21: L2CTL_WPCR Register Diagram
Table 9-22: L2CTL_WPCR Register Fields
Bit No.
(Access)
15:8
WPC1
(R/W)
7:0
WPC0
(R/W)
9–34
15
14
13
12
11
10
0
0
0
0
1
1
31
30
29
28
27
26
25
0
0
0
0
0
0
Bit Name
Write Priority Count 1.
The L2CTL_WPCR.WPC1 bits hold the priority count for L2 bus write channel 0.
Write Priority Count 0.
The L2CTL_WPCR.WPC0 bits hold the priority count for L2 bus write channel 1.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
2
1
1
0
0
0
0
1
1
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
1
0
1
1
WPC0 (R/W)
Write Priority Count 0
16
0
0
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