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ADSP-SC58x PINT Register Descriptions
PINT Pin State Register
When a half port is assigned to a byte in any PINT block, the state of the eight pins (regardless of GPIO or func-
tion, input or output) can be seen in the
register. While neither input nor output drivers of the
PINT_PINSTATE
pin are enabled, reads of the pin state in
PINT_PINSTATE
return zero. The
PINT_PINSTATE
register reports
the inverted state of the pin if the signal inverter is activated by the
PINT_INV_SET
register. The inverter can be
enabled on an individual bit-by-bit basis. Every bit in the
and
register pair
PINT_INV_SET
PINT_INV_CLR
represents a pin signal.
The pin interrupt pin state registers enable the service routine to read the current state of the pin without reading
from GPIO space. If there was an edge-sensitive interrupt, the service routine can check whether the state of the pin
is still high or turned low.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14–95
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