Analog Devices ADSP-SC58 Series Hardware Reference Manual page 408

DMC Features
• Provides page hit detection that supports multiple column accesses to the same row
• User-specified active, precharge, and refresh commands.
• Programmable SDRAM access timing parameters
• Enables automatic refresh generation with programmable refresh intervals
• Self-refresh mode to reduce system power consumption
• Efficient transaction processing to improve throughput and bandwidth using:
• Software programmable SCB IDs to allow SCB ID-based priority
• The ability to postpone up to eight auto-refresh commands
• Software selectable closed page scheme on a per bank basis
• Simple transaction scheduling mechanism to reduce read write turnaround frequency on the memory bus
• Accesses with the same SCB ID are scheduled back-to-back to take advantage of same page access in
SDRAM
• Caching of SDRAM read data burst for specific masters to reduce the latency for same burst accesses.
The DDR2 features are:
• 256M bit to 4G-bit device sizes
• Burst length BL = 4 or 8
• Support for additive latency
• Support for programmable ODT and drive impedance from memory end
• Support for programmable (and ZQ calibration) ODT and drive impedance from the processor end
The DDR 3 features are:
• 512 Mb to 8 Gb device sizes
• Burst length BL = 8
• Support for additive latency
• Support for programmable (and ZQ calibration) ODT and drive impedance
• Support for programmable (and ZQ calibration) ODT and drive impedance from the processor end
The LPDDR features are:
• 64M bit to 2G-bit device sizes
• Burst length BL = 4 or 8
• Support for deep power-down mode
10–2 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference