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Direct Memory Access (DMA/MDMA/EMDMA/CRC)
Clocked by SCLK0 from CGU0 and SCLK1 from CGU1
* See Table 43-12 for values of x associated with specific DMA channels
Figure 1-13: MDMA System Diagram
Extended Memory DMA (EMDMA)
The
Extended Memory DMA (EMDMA)
manner. This includes delay lines, scatter and gather, and circular access types.
Unlike previous SHARC processors which contained external port DMA, the current EPDMA module can access all
memory locations (L1/L2/L3) for source and destination DMA operations.
System MMR Write-Protection (WP158) from SPU
Enable Secure Peripheral (SECUREP158) from SPU
Figure 1-14: EMDMA System Diagram
Cyclic Redundancy Check (CRC)
The
Cyclic Redundancy Check (CRC)
that is presented to the peripheral. The peripheral provides a means to verify periodically the integrity of the system
memory, the contents of memory-mapped registers (MMRs), or communication message objects. It is based on a
CRC32 engine that computes the signature of 32-bit data presented to the peripheral.
The dedicated hardware compares the calculated signature of the operation to a pre-loaded expected signature. If the
two signatures fail to match, the peripheral generates an error. The source channel of the memory-to-memory DMA
channels can provide data. The CRC optionally forwards data to memory through the destination DMA channel.
Alternatively, the peripheral supports data presented by core write transactions.
The CRC peripheral implements a reduced table-look-up algorithm to compute the signature of the data. The CRC
uses a programmable 32-bit CRC polynomial to generate the look-up table (LUT) contents automatically.
More CRC peripheral modes allow for initializing large memory sections with a constant value, or for verifying that
sections of memory are equal to a constant value.
1–8
Automated Descriptor Fetches from Memory
Manual Core Writes to SMMRs
Automated FIFO Reads from Peripherals
Enable Secure Peripheral (SECUREPx) from SPU*
System MMR Write-Protection (WPx) from SPU*
Automated Buffer Reads via SCBs from Memory
engine can be used in applications that copy data in a non-sequential
Automated TCB Fetches from Memory
or
Manual Core Writes to SMMRs
Automated Reads from Memory
Clocked by SCLK0_0
peripheral performs the cyclic redundancy check (CRC) of the block of data
DMA/MDMA
or
MDMA CRC
EMDMA
EMDMA0/1_DONE Transfer Complete Interrupts to SEC/GIC
EMDMA0/1_DONE Trigger Outputs to TRU Slaves
Automated Writes to Memory
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Triggers to/from TRU Slaves/Masters
DMA Data Complete Interrupts to SEC/GIC
DMA Channel Errors to SEC/GIC
Automated Buffer Writes via SCBs to Memory
Automated FIFO Writes to Peripherals
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