Analog Devices ADSP-SC58 Series Hardware Reference Manual page 744

ADSP-SC58x SPI Register Descriptions
Table 16-19: SPI_CTL Register Fields
Bit No.
(Access)
31 MMSE
(R/W)
30 MMWEM
(R/W)
22 SOSI
(R/W)
16–38
Bit Name
Memory-Mapped SPI Enable (Only on SPI2).
When the SPI_CTL.MMSE bit is asserted, communication to an SPI memory device
is automated such that the memory it contains is accessible directly through the read of
processor address space assigned to it. (As far as the SPI peripheral is concerned, this
includes all read accesses received by the SPI peripherals system crossbar slave port.)
Note that when memory-mapped access of SPI memory is enabled, attempts to com-
municate with the SPI device using legacy methods are blocked and receive fabric error
responses are generated. Legacy methods include any direct access made to the Tx and
Rx FIFOs, whether initiated by DMA or processor MMR access.
Memory Mapped Write Error Mask (Only on SPI2).
The SPI_CTL.MMWEM bit specifies whether an error response is returned to the fab-
ric upon write attempts to address space reserved for memory-mapped reads of SPI
memory.
Start on MOSI (Only on SPI2).
The SPI_CTL.SOSI bit is valid only when SPI_CTL.MIOM is enabled for either
DIOM or QIOM, and this bit selects the starting pin and the bit placement on pins
for these modes.
In DIOM, by default, (SPI_CTL.SOSI =0) SPI sends the first bit on the
SPI_MISO pin and the second bit on the SPI_MOSI pin. In QIOM, by default, the
SPI sends the first bit on the SPI_D3 pin, the second bit on the SPI_D2 pin, the
third bit on the SPI_MISO pin and the fourth bit on the SPI_MOSI pin. This order
can be reversed by setting the SPI_CTL.SOSI bit. When this bit is set, the SPI
sends the first bit on the SPI_MOSI pin. The first bit referred to here depends on the
SPI_CTL.LSBF bit setting (MSB bit or LSB bit).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Hardware automated access of memory-mapped SPI
memory disabled.
1 Hardware-automated access of memory-mapped SPI
memory enabled.
0 Write error response returned upon write attempts to
memory-mapped SPI memory
1 Write error response masked (not returned) upon write
attempts to memory-mapped SPI memory
0 Start on MISO (DIOM) or start on SPI_D3 (Only on
SPI2)
1 Start on MOSI