Analog Devices ADSP-SC58 Series Hardware Reference Manual page 194

Table 4-1: Clock Descriptions (Continued)
Clock
SCLK0_1
SCLK1_1
DCLK_1
OCLK_1
CDU_CLKOn
CDU Clock Configuration Options
The CDU Targets table provides information on clock source and destination options.
Table 4-2: CDU Targets
CCLK0_0 SYSCLK_0
CCLK0_0 SYSCLK_0
CCLK1_0 SYSCLK_0
DCLK_0 DCLK_1
OCLK_0 OCLK_1
OCLK_0 OCLK_1
OCLK_0 CCLK0_1
SCLK1_0 SCLK1_1
SCLK0_0 SCLK0_1
OCLK_0/2 CCLK1_1/2
The Peripheral Clock Domains table shows the clock source assigned to each processor peripheral.
Table 4-3: Peripheral Clock Domains
Peripheral
TIMER, CRC0, CRC1, TWI, UART, PORT, PINT, SMC, WDT, EPWM, CNT,
EMAC0, SINC, TMU, HADC, HAE, ACM, MDMA, EMDMA, RTC, CRYPTO AC-
CELERATOR (SPE), DAI, SPORT, SRC, PCG, S/PDIF Rx, S/PDIF Tx, OTPC
QSPI, SPI, EPPI
L2_CTL, SEC, TRU, RCU, SPU, SMPU, CDU, DPM, EBMDMA, MAX BW MDMA,
FFT, MLB, CRYPTO ACCELERATOR (PKA), ROM, CGU
To further illustrate clocking options, the CDU Core Clock Options figure shows the conceptual routing of different
clock sources to each target. Note that all three cores can be clocked by the clocks originating from CGU0. Select
SYS_CLKIN accordingly to get the best match for the core clock frequency.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CDU0 Input
N/A
N/A
N/A
N/A
DCLK_1
DCLK_1
N/A
CCLK0_1
CCLK1_1
CCLK1_1
Description
SCLK0 derived from CGU1
SCLK1 derived from CGU1
DCLK derived from CGU1
OCLK derived from CGU1
Clocks that come out from the CDU that go to different blocks.
CDU0 Output
N/A CDU_CLKO0
N/A CDU_CLKO1
N/A CDU_CLKO2
N/A CDU_CLKO3
N/A CDU_CLKO4
DCLK_0 CDU_CLKO5
N/A CDU_CLKO6
OCLK_0 CDU_CLKO7
DCLK_1 CDU_CLKO8
DCLK_1 CDU_CLKO9
CDU Functional Description
Target
Core1 (SHARC1)
Core2 (SHARC2)
Core0 (ARM A5)
DDR1/2/3
CAN
S/PDIF-RX Ref
Reserved
GigE/RGMII
Link port
SDIO
Clock Source
SCLK0_0
SCLK1_0
SYSCLK_0
4–3