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Channel Timing Control Unit
• Uses the PWM_ACTL.PULSEMODEHI bit to configure pulse position
• Uses the PWM_CHANCFG.POLAH bit to configure polarity
• Generates PWM_AL using
• Uses the
PWM_AL1
• Uses the PWM_ACTL.PULSEMODELO bit to configure pulse position
• Uses the PWM_CHANCFG.POLAL bit to configure polarity
NOTE:
In independent mode, the dead-time insertion is not applicable. The hardware forces dead time to zero.
The PWM_AH and PWM_AL in Independent Operation Mode figure shows an example of the independent mode
of operation where PWM_AH and PWM_AL work from different register bits.
Figure 19-12: PWM_AH and PWM_AL in Independent Operation Mode
PWM_AH and PWM_AL can be positioned in the timer period with a given phase difference between them. Pro-
gram the PWM_ACTL.PULSEMODEHI and PWM_ACTL.PULSEMODELO bits to different values to achieve this
positioning as shown in the Channel Outputs Controlled Independently figure.
19–18
PWM_AL0
register to configure pulse width
PWM_AH0
PWM_AH1
PWM_AH
PWM_AL
PWM_AH and PWM_AL in Independent Mode of operation
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_AL0
PWM_AL1
PULSEMODEHI = 10
POLHI = 1
PULSEMODELO = 01
POLLO = 1
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