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NOTE:
The debugger typically replaces an instruction with a breakpoint instruction for software breakpoints. If a
memory region is protected against write accesses, software breakpoints are not possible unless the SMPU
is configured with the appropriate system master ID of the debugger. The configuration allows it to per-
form a write-access.
In the case where memory is used for data, a read access or cache fill is not possible if the memory is blocked from
read accesses. If read accesses are allowed but write accesses are disallowed, then there is an issue with coherency. The
cache is filled but when the cache is updated and must be written back to the SMPU protected memory, the write-
access is blocked.
In general, practice caution when using both the SMPU and cache.
Speculative Reads
If speculative reads are enabled (SMPU_CTL.RSDIS =0), the SMPU forwards the read transaction directly to the
memory before checking the protection setting corresponding to the addressed memory region. This functionality
saves one clock cycle in the clock domain of the SMPU. The SMPU checks the protection setting while the read
transaction occurs with the memory. If the protection setting dictates that the target memory address is blocked, the
SMPU blocks the read to the master.
If speculative reads are disabled (SMPU_CTL.RSDIS =1), the SMPU checks the protection settings first and for-
wards the transaction to memory only if it passes the configured protection settings. This functionality incurs a one-
cycle latency per read.
Reads affect certain memory operations such as automatic clearing of the memory (that is, FIFOs). When
NOTE:
the SMPU protects this type of memory, disable read speculation since the blocking can occur without the
read transaction reaching the target memory.
ADSP-SC58x SMPU Register List
The System Memory Protection Unit (SMPU) provides selective protection of the processor's memory resources.
The SMPU includes a set of processor events that can be monitored during program execution. A set of registers
governs SMPU operations. For more information on SMPU functionality, see the SMPU register descriptions.
Table 13-2: ADSP-SC58x SMPU Register List
Name
SMPU_BADDR
SMPU_BDTLS
SMPU_CTL
SMPU_EXACADD[n]
SMPU_EXACSTAT[n]
SMPU_IADDR
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Bus Error Address Register
Bus Error Details Register
SMPU Control Register
Exclusive Access IDn Address
Exclusive Access Status
Interrupt Address Register
SMPU Functional Description
13–3
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