Analog Devices ADSP-SC58 Series Hardware Reference Manual page 195

CDU Functional Description
Figure 4-2: CDU Core Clock Options
In the CDU Clock Options - DDR figure, DDR is clocked from the DCLK from CGU0 or CGU1. This configura-
tion provides the flexibility to program the DDR with frequencies orthogonal to the core clock frequencies.
Figure 4-3: CDU Clock Options - DDR
The CAN clock should be a multiple of 500 KHz. Based on this setting, the clock for the CAN module can be
derived either from CGU0 or CGU1. It depends on which CLKIN can provide a frequency in multiples of 500
KHz.
4–4
CGU0
SYS_CLKIN0
CCLK0
CCLK1
SYSCLK
SCLK0
SCLK1
DCLK
OCLK
Clocking Options for SHARC0 core
CGU0
SYS_CLKIN0
CCLK0
CCLK1
SYSCLK
SCLK0
SCLK1
DCLK
OCLK
Clocking Options for SHARC1 core
CGU0
SYS_CLKIN0
CCLK0
CCLK0
SYSCLK
SCLK0
SCLK1
DCLK
OCLK
Clocking Options for ARM core
CGU0
SYS_CLKIN0
CCLK0
CCLK1
SYSCLK
SCLK0
SCLK1
DCLK
OCLK
CGU1
CCLK0
SYS_CLKIN1
CCLK1
SCLK0
SCLK1
DCLK
OCLK
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CLKO0
SHARC0
CLKO1
SHARC1
CLKO2
ARM
CLKO3
DDR