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Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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ADSP-2126x SHARC

Processor

Hardware Reference

Includes ADSP-21261, ADSP-21262

ADSP-21266, ADSP-21267

Revision 5.1, April 2013

Part Number

82-002002-01

Analog Devices, Inc.

One Technology Way

a

Norwood, Mass. 02062-9106

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Page 1: Hardware Reference
® ADSP-2126x SHARC Processor Hardware Reference Includes ADSP-21261, ADSP-21262 ADSP-21266, ADSP-21267 Revision 5.1, April 2013 Part Number 82-002002-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
Manual Contents ............... xxxii What’s New in This Manual ............xxxiv Technical Support ..............xxxiv Supported Processors ..............xxxv Product Information ..............xxxv Analog Devices Web Site ............. xxxvi EngineerZone ..............xxxvi Notation Conventions .............. xxxvii Register Diagram Conventions ..........xxxviii INTRODUCTION Design Advantages ................
Page 4 Contents Processor Core ................ 1-5 Processing Elements ............1-5 Program Sequence Control ..........1-6 Processor Internal Buses ............1-9 Processor Peripherals ............. 1-10 Dual-Ported Internal Memory (SRAM) ......1-10 I/O Processor ..............1-11 Digital Audio Interface (DAI) ........... 1-13 Development Tools ..............1-13 Differences From Previous SHARCs ..........
Page 5 Contents Setting Computational Modes ............. 2-12 32-Bit Floating-Point Format (Normal Word) ......2-12 40-Bit Floating-Point Format ..........2-14 16-Bit Floating-Point Format (Short Word) ......2-14 32-Bit Fixed-Point Format ............. 2-15 Rounding Mode ..............2-15 Using Computational Status ............2-16 Arithmetic Logic Unit (ALU) ............2-17 ALU Operation ..............
Page 6 Contents Secondary Processing Element (PEy) ........... 2-45 Dual Compute Units Sets ............2-47 Dual Register Files ..............2-49 Dual Alternate Registers ............2-50 SIMD and Status Flags ............2-50 SIMD (Computational) Operations ........2-50 PROGRAM SEQUENCER Instruction Pipeline ..............3-4 Instruction Cache .................
Page 7 Contents Loops and Sequencing ..............3-25 Restrictions on Ending Loops ..........3-27 Restrictions on Short Loops ........... 3-28 Loop Address Stack ............... 3-31 Loop Counter Stack .............. 3-32 Reading From LCNTR in a LOOP ........3-36 SIMD Mode and Sequencing ............3-36 Conditional Compute Operations ..........
Page 8 Contents Case #4: External Memory or IOP Memory Space Data Move 3-44 Example: Register-to-Memory Moves – External or IOP Memory Space Data Move ............3-44 Case #5: Uncomplimentary Register Data Move ....3-45 Conditional DAG Operations ..........3-45 Timer and Sequencing ..............3-46 Interrupts and Sequencing ............
Page 9 Contents DAG Operations ................4-9 Addressing With DAGs ............4-10 Data Addressing Stalls ............4-12 Addressing Circular Buffers ........... 4-12 Modifying DAG Registers ............4-17 Addressing in SISD and SIMD Modes ........4-18 DAGs, Registers, and Memory ............ 4-19 DAG Register-to-Bus Alignment ..........4-19 DAG Register Transfer Restrictions ........
Page 10 Contents Internal Memory Data Width ..........5-18 Secondary Processor Element (PEy) ........5-19 Broadcast Register Loads ............5-20 Illegal I/O Processor Register Access ........5-21 Unaligned 64-Bit Memory Access .......... 5-21 Using Memory Access Status ............5-22 Accessing Memory ..............5-22 Access Word Size ..............
Page 11 Contents Short Word Addressing of Dual-Data in SIMD Mode .... 5-38 32-Bit Normal Word Addressing of Single-Data in SISD Mode 5-40 32-Bit Normal Word Addressing of Dual-Data in SISD Mode 5-42 32-Bit Normal Word Addressing of Single-Data in SIMD Mode 5-44 32-Bit Normal Word Addressing of Dual-Data in SIMD Mode 5-46 Extended-Precision Normal Word Addressing of Single-Data ..
Page 12 Contents Boundary Register ..............6-8 Built-In Self-Test Operation (BIST) ........6-9 EMUIDLE Instruction ............6-9 Private Instructions ............... 6-9 References ..................6-9 I/O PROCESSOR General Procedure for Configuring DMA ........7-2 IOP/Core Interaction Options ............7-3 Interrupt-Driven I/O .............. 7-3 Polling/Status Driven I/O ............
Page 13 Contents Setting Up DMA ................ 7-30 PARALLEL PORT Parallel Port Pins ................8-3 Alternate Pin Functions ............8-4 Parallel Ports as FLAG Pins ..........8-4 Parallel Data Acquisition Port as Address Pins ...... 8-5 Parallel Port Operation ..............8-5 Basic Parallel Port External Transaction ........8-5 Reading From an External Device or Memory ......
Page 14 Contents Using the Parallel Port ..............8-17 DMA Transfers ..............8-18 Core Driven Transfers ............8-18 Known Duration Accesses ..........8-20 Status Driven Transfers (Polling) ........8-22 Core-Stall Driven Transfers ..........8-22 Interrupt Driven Accesses ..........8-22 Parallel Port Programming Examples ........... 8-23 SERIAL PORTS Serial Port Signals .................
Page 15 Contents Selecting Frame Sync Options (DIFS) ....... 9-16 Enabling SPORT DMA (SDEN) ........9-17 Interrupt-Driven Data Transfer Mode ......9-17 DMA-Driven Data Transfer Mode ......... 9-17 S Mode ................9-18 S Mode Control Bits ............9-20 Setting the Internal Serial Clock and Frame Sync Rates ..9-20 S Control Bits ..............
Page 16 Contents Clock Signal Options ..............9-33 Frame Sync Options ..............9-34 Framed Versus Unframed Frame Syncs ........9-34 Internal Versus External Frame Syncs ........9-35 Active Low Versus Active High Frame Syncs ......9-36 Sampling Edge for Data and Frame Syncs ......9-36 Early Versus Late Frame Syncs ..........
Page 17 Contents SPORT DMA Parameter Registers ......... 9-69 SPORT DMA Chaining ............ 9-73 Single Word Transfers ............9-73 SPORT Programming Examples ..........9-74 SERIAL PERIPHERAL INTERFACE PORT Functional Description ............... 10-2 SPI Interface Signals ..............10-3 SPI Clock Signal (SPICLK) ..........10-4 SPICLK Timing ..............
Page 18 Contents Slave Mode DMA Operation .......... 10-17 Slave Transfer Preparation ........... 10-18 Changing SPI Configuration ........... 10-20 Switching From Transmit To Receive DMA ..... 10-21 Switching From Receive to Transmit DMA ..... 10-22 DMA Error Interrupts ............ 10-24 DMA Chaining .............. 10-25 SPI Transfer Formats ..............
Page 19 Contents DMA Registers ..............10-39 SPI DMA Internal Index Register (IISPI) ......10-39 SPI DMA Address Modifier Register (IMSPI) ....10-39 SPI DMA Word Count Register (CSPI) ......10-40 Error Signals and Flags .............. 10-40 Mode Fault Error (MME) ............ 10-40 Transmission Error Bit (TUNF) ...........
Page 20 Contents Parallel Data Acquisition Port (PDAP) ........11-6 Masking ................11-8 Packing Unit ................. 11-8 Packing Mode 11 .............. 11-9 Packing Mode 10 .............. 11-9 Packing Mode 01 ............11-10 Packing Mode 00 ............11-10 Clocking Edge Selection ............11-11 Hold Input .................
Page 21 Contents Signal Routing Unit ..............12-3 Connecting Peripherals ............12-3 Pins Interface ................ 12-7 Pin Buffers as Signal Output Pins .......... 12-9 Pin Buffers as Signal Input Pins ........... 12-11 Bidirectional Pin Buffers ............12-12 Making Connections in the SRU ..........12-15 SRU Connection Groups .............
Page 22 Contents Frame Sync Outputs ..............13-4 Frame Sync ................13-4 Frame Sync Output Synchronization with External Clock ..13-5 Phase Shift ................. 13-7 Phase Shift Settings ............... 13-8 Pulse Width ................13-9 Bypass Mode ............... 13-10 Bypass as a Pass Through ..........13-10 Bypass as a One Shot ............
Page 23 Contents SYSTEM DESIGN Pin Descriptions ................. 15-2 Pin Multiplexing ..............15-2 Input Synchronization Delay ..........15-4 Clock Derivation ..............15-4 Power Management Control Register ......... 15-5 RESET and CLKIN .............. 15-7 Reset Generators ..............15-9 Interrupt and Peripheral Timer Pins ........15-12 Core-Based Flag Pins ............
Page 24 Contents SPI Port Booting ..............15-22 32-bit SPI Host Boot ............15-24 16-bit SPI Host Boot ............15-25 8-bit SPI Host Boot ............15-26 Slave Boot Mode ............15-28 Master Boot ..............15-30 Booting From an SPI Flash ..........15-32 Booting From an SPI PROM (16-bit address) ....
Page 25 Contents Program Sequencer Registers ..........A-23 Interrupt Latch Register (IRPTL) ........A-25 Interrupt Mask Register (IMASK) ........A-25 Interrupt Mask Pointer Register (IMASKP) ...... A-26 Interrupt Register (LIRPTL) ..........A-30 Program Counter Register (PC) ........A-33 Program Counter Stack Register (PCSTK) ......A-34 Program Counter Stack Pointer Register (PCSTKP) ..
Page 26 Contents Emulation Registers .............. A-46 Hardware Breakpoint Control Register (BRKCTL) .... A-46 Emulation Control (EMUCTL) Register ......A-50 Breakpoint (PSx, DMx, IOx) Registers ......A-54 EEMUIN Register ............A-58 Enhanced Emulation Status Register (EEMUSTAT) ..A-58 EEMUOUT Register ............A-61 Emulation Clock Counter Registers ........
Page 27 Contents SPORT DMA Count Registers (CSPx) ......A-91 SPORT Chain Pointer Registers (CPSPxx) ......A-91 SPI Registers ................ A-92 SPI Port Status Register (SPISTAT) ........A-92 SPI Port Flags Register (SPIFLG) ........A-95 SPI Control Register (SPICTL) ........A-96 Shift Registers ..............A-100 Receive Shift Register (RXSR) ........
Page 28 Contents Parallel Port DMA Start Internal Index Address Register (IIPP) ..........A-112 Parallel Port DMA Internal Modifier Address Register (IMPP) ..........A-112 Parallel Port DMA Internal Word Count Register (ICPP) ..........A-112 Parallel Port DMA Start External Index Address Register (EIPP) ........A-112 Parallel Port DMA External Modifier Address Register (EMPP) ..........
Page 29 Contents Input Data Port Registers ........... A-148 Input Data Port Control Register (IDP_CTL) ..............A-149 Input Data Port FIFO Register (IDP_FIFO) ............... A-150 Input Data Port DMA Control Registers ......A-152 Parallel Data Acquisition Port Control Register (IDP_PDAP_CTL) ......A-153 Peripheral Timer Registers ..........
Page 30 Contents ADSP-2126x SHARC Processor Hardware Reference...
Page 31: Preface
Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruc- tion set. Programmers who are unfamiliar with Analog Devices processors...
Page 32: Manual Contents
Manual Contents Manual Contents The manual consists of: • Chapter 1, “Introduction” Provides an architectural overview of the ADSP-2126x processor. • Chapter 2, “Processing Elements” Describes the arithmetic/logic units (ALUs), multiplier/accumula- tor units, and shifter. The chapter also discusses data formats, data types, and register files.
Page 33 Preface • Chapter 8, “Parallel Port” Describes the processor’s on-chip DMA controller as a mechanism for transferring data without core interruption. • Chapter 9, “Serial Ports” Describes the six dual data line serial ports. Each SPORT contains a clock, a frame sync, and two data lines that can be configured as either a receiver or transmitter pair.
Page 34: What's New In This Manual
Appendix A, STYKx STYKy “Registers Reference”. Technical Support You can reach Analog Devices processors and DSP technical support in the following ways: • Post your questions in the processors and DSP support community ® at EngineerZone http://ez.analog.com/community/dsp • Submit your questions to technical support directly at: http://www.analog.com/support...
Page 35: Supported Processors
Refer to the CCES or VisualDSP++ online help for a complete list of supported processors. Product Information Product information can be obtained from the Analog Devices Web site and the CCES or VisualDSP++ online help. ADSP-2126x SHARC Processor Hardware Reference...
Page 36: Analog Devices Web Site
Also note, is a free feature of the Analog Devices Web site that myAnalog allows customization of a Web page to display only the latest information about products you are interested in.
Page 37: Notation Conventions
Preface Notation Conventions Text conventions in this manual are identified and described as follows. Example Description File > Close Titles in reference sections indicate the location of an item within the IDE environment’s menu system (for example, the Close command appears on the File menu).
Page 38: Register Diagram Conventions
Register Diagram Conventions Register Diagram Conventions Register diagrams use the following conventions: • The descriptive name of the register appears at the top, followed by the short form of the name in parentheses. • If the register is read-only (RO), write-1-to-set (W1S), or write-1-to-clear (W1C), this information appears under the name.
Page 39 Preface The following figure shows an example of these conventions. Timer Configuration Registers (TIMERx_CONFIG) 15 14 13 12 11 10 Reset = 0x0000 TMODE[1:0] (Timer Mode) ERR_TYP[1:0] (Error Type) - RO 00 - Reset state - unused. 00 - No error. 01 - PWM_OUT mode.
Page 40 Register Diagram Conventions ADSP-2126x SHARC Processor Hardware Reference...
Page 41: Introduction
1 INTRODUCTION A digital signal processor’s data format determines its ability to handle sig- nals of differing precision, dynamic range, and signal-to-noise ratios. Because floating-point DSP math reduces the need for scaling and proba- bility of overflow, using a floating-point DSP can ease algorithm and software development.
Page 42 Design Advantages (SIMD) support, this processor builds on the ADSP-21000 Family pro- cessor core to form a complete system-on-a-chip. The SHARC processor architecture balances a high performance processor core with high performance buses (PM, DM, I/O). In the core, every instruction can execute in a single cycle.
Page 43 Introduction • Extended precision and dynamic range in the computation units • Dual address generators with circular buffering support • Efficient program sequencing Fast, Flexible Arithmetic. The ADSP-21000 family processors execute all instructions in a single cycle. They provide fast cycle times and a complete set of arithmetic operations.
Page 44: Architectural Overview
Architectural Overview High Bandwidth I/O. The processors contain up to a dedicated, 4M bits on-chip ROM, a parallel port, an SPI port, serial ports, Digital Audio Interface (DAI), and JTAG. The DAI incorporates a precision clock gen- erator, input data port, and a signal routing unit. Serial Ports.
Page 45: Processor Core
Introduction The following sections summarize the features of each functional block in the ADSP-2126x architecture. Processor Core The processor core of the ADSP-2126x consists of two processing ele- ments (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruc- tion cache.
Page 46: Program Sequence Control
Architectural Overview Each processing element has a general-purpose data register file that trans- fers data between the computation units and the data buses and stores intermediate results. A register file has two sets (primary and secondary) of 16 general-purpose registers each for fast context switching. All of the reg- isters are 40 bits wide.
Page 47 Introduction sequencer supply addresses for memory accesses. Together the sequencer and data address generators allow computational operations to execute with maximum efficiency since the computation units can be devoted exclusively to processing data. With its instruction cache, the ADSP-2126x can simultaneously fetch an instruction from the cache and access two data operands from memory.
Page 48 commonly used in digital filters and Fourier transforms. The DAGs auto- matically handle address pointer wraparound, reducing overhead, increasing performance, and simplifying implementation. Interrupts. The ADSP-2126x has three external hardware interrupts. The processor also provides three general-purpose interrupts, and a special interrupt for reset.
Page 49: Processor Internal Buses
Introduction Processor Internal Buses The processor core has six buses: PM address, PM data, DM address, DM data, I/O address, and I/O data. The PM bus is used to fetch instructions from memory, but may also be used to fetch data. The DM bus can only be used to fetch data from memory.
Page 50: Processor Peripherals
These registers contain hardware to handle the data width difference. more information, see “Processing Element Registers” on page A-20. Processor Peripherals The term processor peripherals refers to the multiple on-chip functional blocks used to communicate with off-chip devices. The ADSP-2126x peripherals include the JTAG, Parallel, Serial, SPI ports, DAI components (PCG, Timers, and IDP), and any external devices that connect to the processor.
Page 51: I/O Processor
Introduction PM bus for transfers). Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The processor also maintains single-cycle execution when one of the data operands is transferred to or from off-chip, using the processor parallel port.
Page 52 Architectural Overview transmit modes. Serial port clocks and frame syncs can be internally or externally generated. Parallel Port. The ADSP-2126x parallel port provides the processor inter- face to asynchronous 8-bit memory. The parallel port supports a 66M bytes per second transfer rate and 256 word page boundaries. The on-chip DMA controller automatically packs external data into the appropriate word width during transfers.
Page 53: Digital Audio Interface (Dai)
Development Tools The processor is supported by a complete set of software and hardware development tools, including Analog Devices’ emulators and the Cross- Core Embedded Studio or VisualDSP++ development environment. (The emulator hardware that supports other Analog Devices processors also emulates the processor.)
Page 54: Differences From Previous Sharcs
(boards and extenders). In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processors. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Page 55: Processor Core Enhancements
Introduction Processor Core Enhancements Computational bandwidth on the ADSP-2126x processor is significantly greater than that on the ADSP-2106x processors. The increase comes from raising the operational frequency and adding another processing ele- ment: ALU, shifter, multiplier, and register file. The new processing element lets the processor process multiple data streams in parallel (SIMD mode).
Page 56: Memory Organization Enhancements
Differences From Previous SHARCs Memory Organization Enhancements The ADSP-2126x memory map differs from that of the ADSP-2106x DSPs. The system memory map supports double-word transfers each cycle, reflects extended internal memory capacity for derivative designs, and works with an updated control register for SIMD support. The ADSP-2126x family provides enough on-chip memory for several audio decoders.
Page 57 Introduction ADSP-2126x. Instructions, control registers, or other facilities, required to support the new feature set of the ADSP-2116x core include: • Code compatibility to the ADSP-21160 SIMD core • Supersets of the ADSP-2106x programming model • Reserved facilities in the ADSP-2106x programming model •...
Page 58 Differences From Previous SHARCs 1-18 ADSP-2126x SHARC Processor Hardware Reference...
Page 59: Processing Elements
2 PROCESSING ELEMENTS The DSP’s processing elements (PEx and PEy) perform numeric process- ing for DSP algorithms. Each processing element contains a data register file and three computation units—an arithmetic/logic unit (ALU), a mul- tiplier, and a shifter. Computational instructions for these elements include both fixed-point and floating-point operations, and each compu- tational instruction executes in a single cycle.
Page 60 The processor’s assembly language provides access to the data register files in both processing elements. The syntax allows programs to move data to and from these registers, specify a computation’s data format and provide naming conventions for the registers, all at the same time. For information on the data register names, see “Data Register File”...
Page 61: Numeric Formats
Processing Elements PM DATA BUS MODE1 DM DATA BUS REGISTER FILE (16 x 40-BIT) MULTIPLIER SHIFTER MRF2 MRF1 MRF0 ASTATx STKYx TO PROGRAM SEQUENCER Figure 2-1. Computational Block Numeric Formats The DSP supports the 32-bit single-precision floating-point data format defined in the IEEE Standard 754/854. In addition, the DSP supports an extended-precision version of the same format with eight additional bits in the mantissa (40 bits total).
Page 62: Ieee Single-Precision Floating-Point Data Format
Numeric Formats IEEE Single-precision Floating-point Data Format IEEE Standard 754/854 specifies a 32-bit single-precision floating-point format, shown in Figure 2-2. A number in this format consists of a sign bit ( ), a 24-bit significand, and an 8-bit unsigned-magnitude exponent For normalized numbers, the significand consists of a 23-bit fraction f and a “hidden”...
Page 63 Processing Elements The IEEE Standard also provides for several special data types in the sin- gle-precision floating-point format: • An exponent value of 255 (all ones) with a nonzero fraction is a Not-A-Number (NAN). NANs are usually used as flags for data flow control, for the values of uninitialized variables, and for the ...
Page 64: Extended-Precision Floating-Point Format
Numeric Formats Extended-precision Floating-Point Format The extended-precision floating-point format is 40 bits wide, with the same 8-bit exponent as in the IEEE Standard format but a 32-bit signifi- cand. This format is shown in Figure 2-3. In all other respects, the extended-precision floating-point format is the same as the IEEE Standard format.
Page 65: Short Word Floating-Point Format
Processing Elements Short Word Floating-Point Format The DSP supports a 16-bit floating-point data type and provides conver- sion instructions for it. The short float data format has an 11-bit mantissa with a 4-bit exponent plus sign bit, as shown in Figure 2-4.
Page 66 Numeric Formats Table 2-2. FPACK Operations Condition Result 135 < exp Largest magnitude representation. 120 < exp  135 Exponent is Most Significant Bit (MSB) of source exponent concatenated with the three Least Significant Bits (LSBs) of source exponent. The packed fraction is the rounded upper 11 bits of the source fraction.
Page 67: Fixed-Point Formats
Processing Elements During the operation, an overflow sets the condition and FPACK non-overflow clears it. During the operation, the condition is FUNPACK cleared. The conditions are cleared by both instructions. Fixed-Point Formats The DSP supports two 32-bit fixed-point formats—fractional and integer. In both formats, numbers can be signed (twos-complement) or unsigned.
Page 68 Numeric Formats S IG N E D IN T E G E R B IT W E IG H T -2 3 1 2 3 0 2 2 9 • • • • S IG N B IT B IN A R Y P O IN T S IG N E D F R A C T IO N A L B IT W E IG H T...
Page 69 Processing Elements SIGNED INTEGER, NO LEFT SHIFT • • • WEIGHT -2 63 2 62 2 61 • • • • SIGN BINARY POINT SIGNED FRACTIONAL, WITH LEFT SHIFT WEIGHT -2 0 2 -1 2 -2 • • • 2 -61 2 -62 2 -63 •...
Page 70: Setting Computational Modes
Setting Computational Modes Setting Computational Modes register controls the operating mode of the processing ele- MODE1 ments. Table A-2 on page A-5 lists all the bits in . The following bits MODE1 control computational modes: MODE1 • Floating-point data format. Bit 16 ( ) directs the computa- RND32 tional units to round floating-point data to 32 bits (if 1) or round...
Page 71 Processing Elements • The DSP does not provide inexact flags. An inexact flag is an exception flag whose bit position is inexact. The inexact exception occurs if the rounded result of an operation is not identical to the exact (infinitely precise) result. Thus, an inexact exception always occurs when an overflow or an underflow occurs.
Page 72: 40-Bit Floating-Point Format
Setting Computational Modes 40-Bit Floating-Point Format When in extended-precision mode ( bit=0), the DSP supports a RND32 40-bit extended-precision floating-point mode, which has eight additional LSBs of the mantissa and is compliant with the 754/854 standards. How- ever, results in this format are more precise than the IEEE single-precision standard specifies.
Page 73: 32-Bit Fixed-Point Format
Processing Elements 32-Bit Fixed-Point Format The DSP always represents fixed-point numbers in 32 bits, occupying the 32 MSBs in 40-bit data registers. Fixed-point data may be fractional or integer numbers and unsigned or twos-complement. Each computational unit has its own limitations on how these formats may be mixed for a given operation.
Page 74: Using Computational Status
Using Computational Status Though these rounding modes comply with standards set for float- ing-point data, they also apply for fixed-point multiplier operations on fractional data. The same two rounding modes are supported, but only the round-to-nearest operation is actually performed by the multiplier. Using its local result register for fixed-point operations, the multiplier rounds-to-zero by reading only the upper bits of the result and discarding the lower bits.
Page 75: Arithmetic Logic Unit (Alu)
Processing Elements More information on status appears in the sections that ASTAT STKY describe the computational units. For summaries relating instructions and status bits, see Table 2-4, Table 2-5, Table 2-6, Table 2-7, and Table 2-8. Arithmetic Logic Unit (ALU) The ALU performs arithmetic operations on fixed-point or floating-point data and logical operations on fixed-point data.
Page 76: Alu Saturation
Arithmetic Logic Unit (ALU) the ALU operation returns two results, and in compare operations, the ALU operation returns no result (only flags are updated). ALU results can be returned to any location in the register file. The DSP transfers input operands from the register file during the first half of the processor cycle and transfers results to the register file during the second half of the cycle.
Page 77: Alu Status Flags
Processing Elements ALU Status Flags ALU operations update seven status flags in the processing element’s arith- metic status ( ) registers. Table A-4 on page A-12 lists ASTATx ASTATy all the bits in these registers. The following bits in flag ASTATx ASTATy the ALU status (a 1 indicates the condition) of the most recent ALU...
Page 78: Alu Instruction Summary
Arithmetic Logic Unit (ALU) Flag updates occur at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the arithmetic status register or sticky status register explicitly in the same cycle that the ALU is performing an operation, the explicit write to the status register supersedes any flag update from the ALU operation.
Page 79 Processing Elements Table 2-4. Fixed-Point ALU Instruction Summary Instruction ASTATx,y Status Flags STKYx,y Status Flags Fixed-point: AV A AS AI AF C Rn = Rx + Ry – – – – Rn = Rx – Ry – – – – Rn = Rx + Ry + CI –...
Page 80 Arithmetic Logic Unit (ALU) Table 2-5. Floating-Point ALU Instruction Summary Instruction ASTATx,y Status Flags STKYx,y Status Flags Floating-point: AN AC AUS AVS Fn = Fx + Fy – – Fn = Fx – Fy – – Fn = ABS (Fx + Fy) –...
Page 81: Multiply Accumulator (Multiplier)
Processing Elements Multiply Accumulator (Multiplier) The multiplier performs fixed-point or floating-point multiplication and fixed-point multiply/accumulate operations. Fixed-point multiply/accu- mulates are available with either cumulative addition or cumulative subtraction. Multiplier floating-point instructions operate on 32-bit or 40-bit floating-point operands and output 32-bit or 40-bit floating-point results.
Page 82: Multiplier Result Register (Fixed-Point)
Multiply Accumulator (Multiplier) The multiplier transfers input operands during the first half of the proces- sor cycle and transfers results during the second half of the cycle. With this arrangement, the multiplier can read and write the same register file location in a single cycle.
Page 83 Processing Elements MRF2 MRF1 MRF0 OVERFLOW FRACTIONAL RESULT UNDERFLOW OVERFLOW OVERFLOW INTEGER RESULT Figure 2-8. Multiplier Fixed-Point Result Placement register is divided into , and registers, which can MRF2 MRF1 MRF0 be individually read from or written to the register file. Each of these reg- isters has the same format.
Page 84 Multiply Accumulator (Multiplier) In addition to multiplication, fixed-point operations include accumula- tion, rounding, and saturation of fixed-point data. There are three register operations: clear ( ), round ( ), and saturate ( operation ( =0) resets the specified register to zero. Often, it is best to perform this operation at the start of a multiply/accumulate operation to remove results left over from the previous operation.
Page 85: Multiplier Status Flags
Processing Elements Table 2-6. Fixed-Point Format Maximum Values (For Saturation) (Cont’d) Maximum Number (Hexadecimal) MRF2 MRF1 MRF0 Unsigned fractional number 0000 FFFF FFFF FFFF FFFF Unsigned integer number 0000 0000 0000 FFFF FFFF Multiplier Status Flags Multiplier operations update four status flags in the processing element’s arithmetic status registers ( “Arithmetic Status Regis- ASTATx...
Page 86: Multiplier Instruction Summary
Multiply Accumulator (Multiplier) Flag updates occur at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the arithmetic status register or sticky register explicitly in the same cycle that the multiplier is performing an operation, the explicit write to supersedes ASTAT...
Page 87 Processing Elements Table 2-7. Fixed-Point Multiplier Instruction Summary Instruction Input ASTATx,y Flags STKYx,y Flags Mods Fixed-Point: MUS MOS MVS For Input Mods, see Table 2-8 Rn = Rx * Ry – – – MRF = Rx * Ry – – –...
Page 88: Barrel Shifter (Shifter)
Barrel Shifter (Shifter) Table 2-8. Input Modifiers For Fixed-Point Multiplier Instruction Input Input Mods—Options For Fixed-Point Multiplier Instructions Mods from Note the meaning of the following symbols in this table: Table 2-7 Signed inputS Unsigned inputU Integer inputI Fractional inputF Fractional inputs, Rounded outputFR Note that (SF) is the default format for one-input operations, and (SSF) is the default format for two-input operations.
Page 89: Shifter Operation
Processing Elements • Bit field manipulation operations, including extract and deposit • Fixed-point/floating-point conversion operations, including expo- nent extract, number of leading 1s or 0s Shifter Operation The shifter takes from one to three inputs: X input, Y input, and Z input. The inputs (also known as operands) can be any register in the register file.
Page 90 Barrel Shifter (Shifter) Some shifter operations produce 8-bit or 6-bit results. As shown in Figure 2-10, the shifter places these results in either the shf8 field or the bit6 field and sign-extends the results to 32 bits. The shifter always returns a 32-bit result.
Page 91 Processing Elements Rn = FDEP Rx By Ry Figure 2-12 shows bit placement for the following field deposit instruction: R0 = FDEP R1 BY R2; 0X0000 0210 00 00000000 00000000 00000010 00010000 00000000 LEN6 BIT6 LEN6 = 8 BIT6 = 16 00000000 00000000 00000000...
Page 92 Barrel Shifter (Shifter) BIT6 LEN6 RY DETERMINES LENGTH OF BIT FIELD TO TAKE FROM RX AND STARTING POSITION FOR DEPOSIT IN RN LEN6 = NUMBER OF BITS TO TAKE FROM RX, STARTING FROM LSB OF 32-BIT FIELD DEPOSIT FIELD BIT6 REFERENCE POINT BIT6 = STARTING BIT POSITION FOR DEPOSIT, REFERENCED FROM LSB OF 32-BIT FIELD Figure 2-13.
Page 93: Shifter Status Flags
Processing Elements 0x0000 0217 00 00010111 00000000 00000000 00000010 00000000 bit6 len6 len6 = 8 bit6 = 23 0x8788 0000 00 10000111 10000000 00000000 0000000 00000000 Starting bit position for deposit Reference point 00001111 0x0000 000F 00 00000000 00000000 00000000 00000000 Figure 2-14.
Page 94: Shifter Instruction Summary
Barrel Shifter (Shifter) A flag update occurs at the end of the cycle in which the status is gener- ated and is available on the next cycle. If a program writes the arithmetic status register explicitly in the same cycle that the shifter is performing an operation, the explicit write to supersedes any flag update caused by ASTAT...
Page 95 Processing Elements Table 2-10. Shifter Instruction Summary (Cont’d) Instruction ASTATx,y Flags Rn = BCLR Rx BY Ry Rn = BCLR Rx BY <data8> Rn = BSET Rx BY Ry Rn = BSET Rx BY <data8> Rn = BTGL Rx BY Ry Rn = BTGL Rx BY <data8>...
Page 96: Data Register File
Data Register File Data Register File Each of the DSP’s processing elements has a data register file, which is a set of data registers that transfers data between the data buses and the computational units. These registers also provide local storage for oper- ands and results.
Page 97 Processing Elements 5. PEx Multiplier 6. PEy Multiplier 7. PEx Shifter 8. PEy Shifter The data register file in Figure 2-1 on page 2-3 lists register names of through within the PEx’s register file. When a program refers to these registers as through , the computational units treat the contents of...
Page 98: Alternate (Secondary) Data Registers
Alternate (Secondary) Data Registers • through always refer to PEy registers for data move instruc- tions, whether the DSP is in SISD or SIMD mode. For more information on SISD and SIMD computational operations, see “Secondary Processing Element (PEy)” on page 2-45.
Page 99: Multifunction Computations
Processing Elements results in either , without regard to the state of the regis- MODE1 ter. With this arrangement, code can use the result registers as primary and alternate accumulators, or code can use these registers as two parallel accumulators. This feature facilitates complex math. register controls the access to alternate registers.
Page 100 Multifunction Computations way as the single function computations, except that in the dual add/sub- tract computation, the ALU flags from the two operations are ORed together. To work with the available data paths, the computational units constrain which data registers hold the four input operands for multifunction com- putations.
Page 101 Processing Elements NOTE THAT SHIFTER IS PM DATA BUS MODE1 NOT AVAILABLE FOR MULTIFUNCTION INSTRUCTIONS. DM DATA BUS REGISTER FILE (16 x 40-BIT) MULTIPLIER SHIFTER MRF2 MRF1 MRF0 ASTATX STKYX TO PROGRAM SEQUENCER Figure 2-15. Input Registers for Multifunction Computations (ALU and Multiplier) •...
Page 102 Multifunction Computations Table 2-12. Fixed-Point Multiply and Add, Subtract, Or Average (Any combination of left and right column) Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 – R15-12 Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12)/2 MRF = MRF –...
Page 103: Secondary Processing Element (Pey)
Processing Elements Or, the DSP can perform the following result register transfer and parallel read: R5 = MR1F, R6 = DM(I1,M2); Secondary Processing Element (PEy) The ADSP-2126x contains two sets of computational units and associated register files. As shown in Figure 2-16, these two processing elements (PEx and PEy) support SIMD operation.
Page 104 Secondary Processing Element (PEy) using only PEx. When the bit is set (1), the ADSP-2126x operates PEYEN in SIMD mode, using the PEx and PEy processing elements. There is a one cycle delay after is set or cleared, before the change to or from PEYEN SIMD mode takes effect.
Page 105: Dual Compute Units Sets
Processing Elements Dual Compute Units Sets The computational units (ALU, multiplier, and shifter) in PEx and PEy are identical. The data bus connections for the dual computational units permit asymmetric data moves to, from, and between the two processing elements. Identical instructions execute on the PEx and PEy computa- tional units;...
Page 106 Secondary Processing Element (PEy) Table 2-15. SIMD Mode Complementary Register Pairs (Cont’d) ASTATx ASTATy STKYx STKYy Table 2-16. Other Complementary Register Pairs USTAT1 USTAT2 USTAT3 USTAT4 MSB1 1 These register pairs are not directly accessible by instruc- tions. However, these registers can be read using the mul- tiplier operation MRxF/B = Rn/Rn = MRxF/B.
Page 107: Dual Register Files
Processing Elements Dual Register Files The operand, result busing, and porting are identical in the two 16 entry data register files (one in each PE). The same is true for each 16 entry alternate register files. The transfer direction, data bus, source and destina- tion registers and usage depend on the following conditions: •...
Page 108: Dual Alternate Registers
Secondary Processing Element (PEy) Dual Alternate Registers Both register files consist of a primary set of 16 by 40-bit registers and an alternate set of 16 by 40-bit registers. Context switching between the two sets of registers occurs in parallel between the two processing elements. For more information, see “Alternate (Secondary) Data Registers”...
Page 109 Processing Elements In SISD mode ( bit=0), the register-to-register transfers are unidirec- PEYEN tional, meaning that an operation performed on one processing element is not duplicated on the other processing element. The SISD transfer uses a source register and a destination register. Either register can be in either element’s data register file.
Page 110 Secondary Processing Element (PEy) Even if the code uses a conditional operation to select whether the transfer occurs, only the explicit transfer can take place if the desti- nation register has no complement. In the case where a DAG, control, or status register is both source and des- tination, the data move operation executes the same as if SIMD mode were disabled.
Page 111 Processing Elements Table 2-17. Register-to-Register Move Summary (SISD Versus SIMD) Mode Instruction Explicit Transfer Implicit Transfer Executed According Executed According to PEx to PEx IF condition compute, Rx = Ry; Rx loaded from Ry None SISD IF condition compute, Rx = Sy; Rx loaded from Sy None IF condition compute, Sx = Ry;...
Page 112 Secondary Processing Element (PEy) 2-54 ADSP-2126x SHARC Processor Hardware Reference...
Page 113: Program Sequencer
3 PROGRAM SEQUENCER The DSP’s program sequencer controls program flow by constantly pro- viding the address of the next instruction to be fetched for execution. Program flow in the DSP is mostly linear, with the processor executing instructions sequentially. This linear flow varies occasionally when the program branches due to nonsequential program structures, such as those shown below.
Page 114 The sequencer uses the blocks shown in Figure 3-1 to execute instruc- tions. The sequencer’s address multiplexer selects the value of the next fetch address from several possible sources. The fetched address enters the instruction pipeline, made up of the fetch address register, decode address register, and program counter ( ) register.
Page 115 Program Sequencer INSTRUCTION CACHE FLAGS CONDITION LOOP CONTROL LOGIC CORE TIMER OTHER INTERRUPTS INSTRUCTION PIPELINE INTERRUPT PROGRAM CONTROLLER COUNTER STACK NEXT ADDRESS MULTIPLEXER PM ADDRESS BUS PM DATA BUS Figure 3-1. Program Sequencer Block Diagram ADSP-2126x SHARC Processor Hardware Reference...
Page 116: Instruction Pipeline
Instruction Pipeline Instruction Pipeline The program sequencer determines the next instruction address by exam- ining both the current instruction being executed and the current state of the processor. If no conditions require otherwise, the DSP fetches and exe- cutes instructions from memory in sequential order. To achieve a high execution rate while maintaining a simple programming mode, the DSP employs a three stage pipeline to process instructions: 1.
Page 117: Instruction Cache
Program Sequencer • Jumps • Subroutine calls and returns • Interrupts and returns • Loops CLOCK CYCLES EXECUTE 0x08 0x09 0x0A INSTRUCTION DECODE INSTRUCTION 0x09 0x08 0x0A 0x0B FETCH INSTRUCTION 0x08 0x09 0x0A 0x0B 0x0C Figure 3-2. Pipelined Execution Cycles Instruction Cache Usually, the sequencer fetches an instruction from memory on each cycle.
Page 118 Instruction Cache A bus conflict occurs when the PM data bus, normally used to fetch an instruction in each cycle, is used to fetch instruction and to access data. Because of the three stage instruction pipeline, as the DSP executes an instruction (at address n) it also uses the PM bus to access data.
Page 119: Block Conflicts
Program Sequencer The cache places instructions in entries according to the four LSBs of the instruction’s address. When the sequencer checks for an instruction to fetch from the cache, it uses the four address LSBs as an index to a cache set.
Page 120: Using The Cache
Instruction Cache are made to the same block in internal memory. This scenario occurs when data is accessed from the same block from which the instructions are executed. This scenario also occurs when an instruction performs both a DM and PM access to the same block in one instruction. In the first case, the instruction takes two cycles to complete, with the data being accessed in the first cycle and the instruction in the second.
Page 121: Optimizing Cache Usage
Program Sequencer cache hit. The same instruction does generate a hit and can be taken from the cache after the cache is enabled. If the cache freeze bit of the register is set by a program memory MODE2 data access instruction n, then the n+2 instruction is cached. This results from the effect latency of the register.
Page 122 Instruction Cache An example of inefficient cache code appears in Table 3-1. The PM bus data access at address 0x101 in the loop, , causes a bus conflict and Outer also causes the cache to load the instruction being fetched at 0x103 (into set 3).
Page 123: Branches And Sequencing
Program Sequencer Table 3-1. Cache Inefficient Code (Cont’d) Address Instruction 0x021F rts; Branches and Sequencing One type of nonsequential program flow that the sequencer supports is branching. A branch occurs when a instruction JUMP CALL RETURN moves execution to a location other than the next sequential address. For descriptions on how to use instructions, see SHARC JUMP...
Page 124: Conditional Branches
Branches and Sequencing 2. Pops the status stack if the status registers that ASTATx/y MODE1 have been pushed for interrupts or timers. IRQ2-0 There are a number of parameters that can be specified for branching instructions: • Branches can be direct or indirect. For direct branches, the sequencer generates the address;...
Page 125: Delayed Branches
Program Sequencer Delayed Branches The instruction pipeline influences how the sequencer handles delayed branches. For immediate branches in which JUMP CALL RETURN instructions are not specified as delayed branches , two instruction (DB) cycles are lost ( ) as the pipeline empties and refills with instructions from the new branch.
Page 126 Branches and Sequencing In delayed branch, instructions that use the delayed JUMP CALL RETURN branches modifier, no instruction cycles are lost in the pipeline. This (DB) is because the DSP executes the two instructions after the branch while the pipeline fills with instructions from the new location. This is shown in the sample code below.
Page 127 Program Sequencer Besides being more challenging to code, delayed branches impose some limitations that stem from the instruction pipeline architecture. Because the delayed branch instruction and the two instructions that follow it must execute sequentially, the instructions in the two locations that follow a delayed branch instruction cannot be: •...
Page 128: Loop And Status Stacks And Sequencing
Loop and Status Stacks and Sequencing following example, instruction 2 immediately follows instruction 1 in all occasions: jump (pc, 3) (db): instruction 1 instruction 2;  During a delayed branch, a program can read the stack register stack pointer register. This read shows that the return address on the PC stack has already been pushed or popped, even though the branch has not yet occurred.
Page 129: Conditional Sequencing
Program Sequencer • PC stack full. Bit 21 ( ) indicates that the PC stack is full (if 1) PCFL or not full (if 0)—not a sticky bit, cleared by a • PC stack empty. Bit 22 ( ) indicates that the PC stack is empty PCEM (if 1) or not empty (if 0)—not sticky, cleared by a PUSH...
Page 130 Conditional Sequencing ), the mode control 1 register ( ), the flag inputs, ASTATx ASTATy MODE1 and the loop counter. For more information on arithmetic status, see “Using Computational Status” on page 2-16. When in SIMD mode, con- ditional execution is effected by the arithmetic status of both processing elements.
Page 131 Program Sequencer Table 3-6. IF Condition and DO/UNTIL Termination Mnemonics Condition From Description True if… Mnemonic ALU = 0 AZ = 1 ALU  0 AZ = 0 ALU > 0 footnote ALU < zero footnote ALU  0 footnote ALU ...
Page 132 Conditional Sequencing Table 3-6. IF Condition and DO/UNTIL Termination Mnemonics (Cont’d) Condition From Description True if… Mnemonic Flag Input Flag0 asserted FI0 = 1 FLAG0_IN Flag0 not asserted FI0 = 0 NOT FLAG0_IN Flag1 asserted FI1 = 1 FLAG1_IN Flag1 not asserted FI1 = 0 NOT FLAG1_IN Flag2 asserted...
Page 133: Core Stalls
Program Sequencer Core Stalls Like all previous SHARC processors, there are a number of conditions that cause the core to temporarily stop fetching and executing further instructions. This event, known as a core stall, occurs when an instruction accesses a peripheral’s data-buffer. Specifically, the core stalls when it reads an empty receive buffer or writes a full transmit buffer.
Page 134 Core Stalls Table 3-7. System/Emulator Memory-Mapped Registers Register Address Register Address EEMUIN 0x30020 PSA4S 0x300A6 EEMUSTAT 0x30021 PSA4E 0x300A7 EEMUOUT 0x30022 DMA1S 0x300B2 SYSCTL 0x30024 DMA1E 0x300B3 BRKCTL 0x30025 DMA2S 0x300B4 REVPID 0x30026 DMA2E 0x300B5 PSA1S 0x300A0 PMDAS 0x300B8 PSA1E 0x300A1 PMDAE 0x300B9...
Page 135: Execution Stalls
Program Sequencer The stall occurs during the decode phase of Instruction 3. Instruc- tion 3 takes two cycles to complete decode. Execution Stalls The following events can cause an execution stall for the ADSP-2126x: • One cycle on a Program Memory Data Access with instruction cache miss •...
Page 136: Dag Stalls
Core Stalls • Any read reference to a memory-mapped register located within a peripheral such as the SPI, SPORTS, IDP, or parallel port requires a minimum of four cycles; so the minimum stall is three cycles. • Any reference to a memory-mapped register in a conditional instruction stalls the processor for one extra cycle (with respect to an unconditional instruction).
Page 137: Loops And Sequencing
Program Sequencer • TCB loading takes 16 core clock cycles to configure 4 IOP regis- ters. This access is not divisible. Loops and Sequencing Another type of nonsequential program flow that the sequencer supports is looping. A loop occurs when a instruction causes the DSP to UNTIL repeat a sequence of instructions until a condition tests true.
Page 138 Loops and Sequencing When executing a instruction, the program sequencer pushes the UNTIL address of the loop’s last instruction and its termination condition onto the loop address stack. The sequencer also pushes the top-of-loop address—the address of the instruction following the instruc- DO/UNTIL tion—onto the PC stack.
Page 139: Restrictions On Ending Loops
Program Sequencer Table 3-8. Pipelined Execution Cycles for Loop Back (Iteration) Cycles Execute E – 1 E – 2 Decode E – 1 B + 1 Fetch B + 1 B + 2 E is the loop end instruction, and B is the loop start instruction. 1.
Page 140: Restrictions On Short Loops
Loops and Sequencing • An instruction that writes to the loop counter from memory can- not be used as the third-to-last instruction of a counter-based loop (at e–2, where e is the end-of-loop address). • An instruction cannot be used as the instruction that IF NOT LCE follows a write to from memory.
Page 141 Program Sequencer iterate only once or twice and loops of length two that iterate only once incur two cycles of overhead, because two aborted instructions after the last iteration are needed to clear the instruction pipeline. Table 3-10. Pipelined Execution Cycles for Single Instruction Counter-based Loop with Three Iterations Cycles Execute...
Page 142 Loops and Sequencing Table 3-12. Pipelined Execution Cycles for Two Instruction Counterbased Loop with Two Iterations Cycles Execute N + 1 (Pass 1) N + 2 (Pass 1) N + 1 (Pass 2) N + 2 (Pass 2) N + 3 Decode N + 1 N + 21...
Page 143: Loop Address Stack
Program Sequencer Similarly, in a one instruction loop that iterates at least three times, pro- cessing is delayed by one cycle if the interrupt occurs during the third-to-last iteration. For more information on pipeline execution during interrupts, see “Interrupts and Sequencing” on page 3-48.
Page 144: Loop Counter Stack
Loops and Sequencing register contains the top entry on the loop address stack. This LADDR register is readable and writable over the DM data bus. Reading from and writing to does not move the loop address stack pointer; only a LADDR stack push or pop performed with explicit instructions moves the stack pointer.
Page 145 Program Sequencer same empty and overflow status flags from the register apply to both STKYx stacks. The loop counter stack is six locations deep. The stack is full when all entries are occupied, is empty when no entries are occupied, and is over- flowed if a push occurs when the stack is already full.
Page 146 Loops and Sequencing loop. If there is no executing loop, the value of is 0xFFFF FFFF CURLCNTR after the pop. Writing does not cause a stack push. If a program writes a new CURLCNTR value to , the program changes the count value of the loop cur- CURLCNTR rently executing.
Page 147 Program Sequencer LCNTR AAAA AAAA CURLCNTR 0XFFFF FFFF AAAA AAAA CURLCNTR AAAA AAAA AAAA AAAA LCNTR BBBB BBBB CURLCNTR BBBB BBBB LCNTR LCNTR CCCC CCCC AAAA AAAA AAAA AAAA AAAA AAAA BBBB BBBB BBBB BBBB BBBB BBBB CURLCNTR CCCC CCCC CCCC CCCC CCCC CCCC DDDD DDDD...
Page 148: Reading From Lcntr In A Loop
SIMD Mode and Sequencing Reading From LCNTR in a LOOP If a program reads during the last two instructions of a terminating LCNTR loop, the value of is the last value for the loop. For LCNTR CURLCNTR example: R12=0x8; LCNTR = R12, do (PC,7) until lce; nop;...
Page 149 Program Sequencer and are not duplicated in . In SIMD mode, the status stack STKYx STKYy stores both values. A status stack instruc- ASTATx ASTATy PUSH tion in SIMD mode affects both registers in parallel. While in SIMD mode, the sequencer evaluates conditions from both pro- cessing elements for conditional ( ) and loop ( ) instructions.
Page 150: Conditional Compute Operations
SIMD Mode and Sequencing Conditional Compute Operations While in SIMD mode, a conditional compute operation can execute on both processing elements, either element, or neither element, depending on the outcome of the status flag test. Flag testing is independently per- formed on each processing element.
Page 151: Case #1: Complementary Register Pair Data Move
Program Sequencer Case #1: Complementary Register Pair Data Move In this case, data moves from a complementary register pair to a comple- mentary register pair. The DSP executes the explicit move depending on the evaluation of the conditional test in the PEx processing element and the implicit move depending on the evaluation of the conditional test in the PEy processing element.
Page 152: Example 2: Register Move - Pey Explicit Register
SIMD Mode and Sequencing Example 2: Register Move – PEy Explicit Register For this instruction, the DSP is operating in SIMD mode, a register in the PEy data register file is the explicit register and is pointing to an even address in internal memory.
Page 153: Example 4: Register-To-Memory Move - Pey Explicit Register
Program Sequencer Table 3-17. Register-to-Register Moves – Complementary Pairs Condition Condition Result in PEx in PEy Explicit Implicit No data move occurs No data move occurs No data move to registers r9, s2 transfers to registers s9, px2 and px1, and ustat1 occurs ustat2 r2 transfers to registers r9, No data move to s9, px2, or ustat2...
Page 154: Case #2: Uncomplimentary-To-Complementary Register Move
SIMD Mode and Sequencing Table 3-18. Register-to-Register Moves – Complementary Register Pairs Condition Condition Result in PEx in PEy Explicit Implicit s2 transfers to registers r9, NO data move to registers s9, px1, and ustat1 px2, and ustat2 occurs s2 transfers to registers r9, r2 transfers to registers s9, px2, px1, and ustat1 and ustat2...
Page 155: Case #3: Complementary-To-Uncomplimentary Register Move
Program Sequencer Table 3-19. Uncomplimentary-to-Complementary Register Move Condition Condition Result in PEx in PEy Explicit Implicit r1 remains unchanged s1 remains unchanged r1 remains unchanged s1 gets px value r1 gets px value s1 remains unchanged r1 gets px value s1 gets px value Case #3: Complementary-to-Uncomplimentary Register Move...
Page 156: Case #4: External Memory Or Iop Memory Space Data Move
SIMD Mode and Sequencing DAG to DAG move: if EQ m1 = i15; Complimented register to DAG move: if EQ i6 = r9; In all the cases described above, the behavior is the same. If the condition in PEx is true, then only the transfer occurs. Table 3-20.
Page 157: Case #5: Uncomplimentary Register Data Move
Program Sequencer indirect addressing. However, the same results occur using direct addressing. IF EQ DM(I0,M0) = R2; IF EQ DM(I0,M0) = S2; Case #5: Uncomplimentary Register Data Move In the case of memory-to-DAG register moves, the transfer does not occur when both PEx and PEy are false.
Page 158: Timer And Sequencing
Timer and Sequencing Timer and Sequencing The sequencer includes a programmable interval timer, which appears in Figure 3-1 on page 3-3. Bits in the , and registers MODE2 TCOUNT TPERIOD control timer operations as described below. • Timer enable Bit 5 ( ).
Page 159 Program Sequencer When a program enables the timer, the timer starts decrementing the register at the end of the next clock cycle. If the timer is subse- TCOUNT quently disabled, the timer stops decrementing after the next clock TCOUNT cycle as shown in Figure 3-5.
Page 160: Interrupts And Sequencing
Interrupts and Sequencing loading from and the timer’s decrementing of TCOUNT TPERIOD TCOUNT Also note that are not initialized at reset. Programs TCOUNT TPERIOD should initialize these registers before enabling the timer. Interrupts and Sequencing Another type of nonsequential program flow that the sequencer supports is interrupt processing.
Page 161 Program Sequencer this table are spaced at 4-instruction intervals. Each interrupt vector has associated latch and mask bits. For a list of interrupt vector addresses and their associated latch and mask bits, see Table B-2 on page B-2. “Interrupt Register (LIRPTL)” on page A-30, “Interrupt Mask Register (IMASK)”...
Page 162 Interrupts and Sequencing Except for reset, all interrupt service routines should end with a return-from-interrupt ( ) instruction. After reset, the PC stack is empty, so there is no return address. The last instruction of the reset service rou- tine should be a to the start of the program.
Page 163 Program Sequencer Table 3-22. Pipelined Execution Cycles for Interrupt During Delayed Branch Instruction Cycles Execute N + 1 N + 2 N – 1 Decode N + 1 N + 2 V + 1 J–>NOP J + 1–>NOP Fetch N + 1 V + 1 V + 2 N + 2...
Page 164: Delayed Interrupt Processing
Interrupts and Sequencing latency associated with the interrupts. If an interrupt is latched by IRQ2–0 explicitly writing into the register, then two instructions are exe- IRPTL cuted after that cycle in which is written. IRPTL If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the higher priority interrupt is delayed by one additional cycle.
Page 165: Sensing Interrupts
Program Sequencer Sensing Interrupts For external interrupt pins , the DSP supports two types of inter- IRQ2–0 rupt sensitivity—edge-sensitive and level-sensitive. The DSP detects a level-sensitive interrupt if the signal input is low (active) when sampled on the rising edge of /2.
Page 166: Masking Interrupts
Interrupts and Sequencing Table A-3 on page A-8 lists all of the bits in the register. MODE2 The DSP accepts external interrupts that are asynchronous to the DSP’s core clock ( ), allowing external interrupt signals to change at any CLCK time.
Page 167: Latching Interrupts
Program Sequencer Latching Interrupts When the DSP recognizes an interrupt, the DSP’s interrupt latch ( IRPTL ) registers set a bit (latch) to record that the interrupt occurred. LIRPTL The bits in these registers indicate all interrupts that are currently being serviced or are pending.
Page 168: Stacking Status During Interrupts
Interrupts and Sequencing registers. Table A-5 on page A-18 lists the bits in these registers. Service routines for arithmetic interrupts must clear the appropriate STKYx bits to clear the interrupt. If the bits are not cleared, the interrupt is STKYy still active after the return from interrupt ( ...
Page 169 Program Sequencer push occurs when the stack is already full. Bits in the register indi- STKYx cate the status stack full and empty states as describe below. • Status stack overflow. Bit 23 ( ) indicates that the status stack SSOV is overflowed (if 1) or not overflowed (if 0)—a sticky bit.
Page 170: Nesting Interrupts
Interrupts and Sequencing Nesting Interrupts The sequencer supports interrupt nesting—responding to another inter- rupt while a previous interrupt is being serviced. Bits in the MODE1 IMASKP registers control interrupt nesting as described below. LIRPTL • Interrupt Nesting enable. Bit 11 ( ).
Page 171 Program Sequencer Programs should change the interrupt nesting enable ( ) bit only NESTM while outside of an interrupt service routine or during the reset service routine. If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the higher priority interrupt is delayed by one cycle.
Page 172: Reusing Interrupts
Interrupts and Sequencing Reusing Interrupts When an interrupt occurs, the sequencer sets the corresponding bit in the register. During execution of the service routine, the sequencer IRPTL keeps this bit cleared—the DSP clears the bit during every cycle, prevent- ing the same interrupt from being latched while its service routine is already executing.
Page 173: Interrupting Idle
Program Sequencer Interrupting IDLE The sequencer supports placing the DSP in —a special instruction IDLE that halts the processor core in a low power state. The halt occurs until any interrupt is latched, serviced, and then returned from using the instruction.
Page 174 Summary STKYX ASTATX ASTATY MODE1 MODE2 STKYY MMASK INSTRUCTION CACHE INPUT FLAGS INSTRUCTION LOOP ADDRESS LATCH STACK (LADDR) CONDITION LOOP COUNT STACK LOGIC (CURLCNTR, LCNTR) LOOP CONTROL CORE TIMER BRANCH CONTROL ADDRESS FROM DAG2 TMREXP OTHER INTERRUPTS INSTRUCTION PIPELINE INTERRUPT PROGRAM FETCH DECODE...
Page 175 Program Sequencer Table 3-24 Table 3-25 list the registers within and related to the pro- gram sequencer. All registers in the program sequencer are universal registers ( ), so they are accessible to other universal registers and to Uregs data memory. All of the sequencer’s registers and the top of stacks are readable and writable, except for the fetch address, decode address, and PC.
Page 176 Summary Table 3-24. Sequencer Registers Read and Effect Latencies Register Contents Bits Read Effect Latency Latency FADDR Fetch address — — DADDR Decode address — — Execute address — — PCSTK Top of PC stack PCSTKP PC stack pointer LADDER Top of loop address stack CURLCNTR Top of loop count stack (current loop...
Page 177 Program Sequencer Table 3-25. System Registers Read and Effect Latencies (Cont’d) Register Contents Bits Read Maximum Latency Effect Latency STKYY Sticky status flags USTAT1 User-defined status flags USTAT2 User-defined status flags USTAT3 User-defined status flags USTAT4 User-defined status flags 1 Note that the number of cycles it takes for the effect latencies for different registers (for example, MODE1, MODE2) given above is just a maximum value.
Page 178 Summary 3-66 ADSP-2126x SHARC Processor Hardware Reference...
Page 179: Data Address Generators
4 DATA ADDRESS GENERATORS The DSP’s Data Address Generators (DAGs) generate addresses for data moves to and from Data Memory (DM) and Program Memory (PM). By generating addresses, the DAGs let programs refer to addresses indirectly, using a DAG register instead of an absolute address. The DAGs architec- ture, which appears in Figure 4-1, supports several functions that...
Page 180 As shown in Figure 4-1, each DAG has four types of registers. These regis- ters hold the values that the DAG uses for generating addresses. The four types of registers are: • Index registers (I0–I7 for DAG1 and I8–I15 for DAG2). An index register holds an address and acts as a pointer to memory.
Page 181 Data Address Generators DM/PM DATA BUS FROM INSTRUCTION REGISTERS REGISTERS REGISTERS REGISTERS 8 X 32 8 X 32 8 X 32 8 X 32 MODULAR LOGIC FOR INTERRUPTS MODE1 FOR BITREV INSTRUCTION STKYX UPDATE BIT-REVERSE I0 (DAG1) OR I8 (DAG2) ONLY. (OPTIONAL) FOR ALL I REGISTERS USING BITREV INSTRUCTIONS...
Page 182: Setting Dag Modes
Setting DAG Modes Setting DAG Modes register controls the operating mode of the DAGs as described MODE1 below. • Circular buffering enable. Bit 24 ( ) enables (if 1) or disables CBUFEN (if 0) circular buffering. • Broadcast register loading enable, DAG1-I1. Bit 23 ( BDCST1 enables register broadcast loads to complementary registers from indexed moves (if 1) or disables broadcast loads (if 0).
Page 183: Circular Buffering Mode
Data Address Generators Circular Buffering Mode bit in the register enables circular buffering—a mode CBUFEN MODE1 where the DAG supplies addresses that range within a constrained buffer length (set with an register). Circular buffers start at a base address (set with a register), and increment addresses on each access by a modify value (set with an...
Page 184: Alternate (Secondary) Dag Registers
Setting DAG Modes register load operation on both processing elements with register load broadcasting enabled. In Table 4-1, note that are complemen- tary data registers. Note also that the letters a and b (as in Ma or Mb) indicate numbers for modify registers in DAG1 and DAG2. The letter a indicates a DAG1 register and can be replaced with 0 through 7.
Page 185 Data Address Generators Bits in the register can activate alternate register sets within the MODE1 DAGs: the lower half of DAG1 ( ), the upper half of DAG1 B0–3 ), the lower half of DAG2 ( ), and the upper half B4–7 B8–11 of DAG2 (...
Page 186: Bit-Reverse Addressing Mode
Setting DAG Modes alternate registers may be accessed. Note that programs should use a instruction for the wait period. BIT SET MODE1 SRD1L; /* Activate alternate dag1 lo regs */ NOP; /* Wait for access to alternates */ R0 = DM(i0,m1); Bit-Reverse Addressing Mode bits in the register enable the bit-reverse addressing...
Page 187: Using Dag Status
Data Address Generators Using DAG Status The DAGs can provide addressing for a constrained range of addresses, repeatedly cycling through this data (or buffer). A buffer overflow (or wraparound) occurs each time the DAG circles past the buffer’s base address. (See “Addressing Circular Buffers”...
Page 188: Addressing With Dags
DAG Operations • “Addressing With DAGs” on page 4-10 • “Data Addressing Stalls” on page 4-12 • “Addressing Circular Buffers” on page 4-12 • “Modifying DAG Registers” on page 4-17 An important item to note from Figure 4-1 is that the DAG automatically adjusts the output address per the word size of the address location (short word, normal word, or long word).
Page 189 Data Address Generators By comparison, the following instruction accesses the program memory location indicated by the value and does not change the value in R6 = PM(M12,I15); /* Pre-modify addressing without update */ POST-MODIFY PRE-MOD IFY I REGISTER UPDATE NO I REGISTER UPDATE SYNTAX: PM(MX, IX) SYNTAX:...
Page 190: Data Addressing Stalls
DAG Operations The following example instruction accepts up to 6-bit modifiers: F6 = F1 + F2,PM(I8,0x0B) = ASTAT; /* PM address = I8, I8 = I8 + 0x0B */  Note that pre-modify addressing operations must not change the memory space of the address. Data Addressing Stalls As explained in the previous sections, the instruction sequence stalls for one cycle if a read-after-write hazard is detected on a DAG register.
Page 191 Data Address Generators updating the index on each access with a positive or negative modify value register or immediate value). If the index pointer falls outside the buf- fer, the DAG subtracts from or adds to the length of the buffer value, wrapping the index pointer back to the start of the buffer.
Page 192 DAG Operations 3. Load the buffer’s length into the corresponding register. For example, corresponds to 4. Load the modify value (step size) into an register in the corre- sponding DAG. For example, through correspond to Alternatively, the program can use an immediate value for the modifier.
Page 193 Data Address Generators THE FOLLOWING SYNTAX SETS UP AND ACCESSES A CIRCULAR BUFFER WITH: LENGTH = 11 BASE ADDRESS = 0X80500 MODIFIER = 4 BIT SET MODE1 CBUFEN; /* ENABLES CIRCULAR BUFFER ADDRESSING; SET BY DEFAULT */ B0 = 0X80500; /* LOADS B0 AND L0 REGISTERS WITH BASE ADDRESS */ L0 = 11;...
Page 194 DAG Operations • If M is positive: + M if I + M < buffer base (start of buffer)  + M – L if I buffer base + length (end of buffer) • If M is negative:  + M if I buffer base (start of buffer) + M + L if I + M <...
Page 195: Modifying Dag Registers
Data Address Generators There is one set of registers ( ) in each DAG that can generate an interrupt on circular buffer overflow (address wraparound). For more information, see “Using DAG Status” on page 4-9. When a program needs to use without circular buffering and the DSP has the circular buffer overflow interrupts unmasked, the program should disable the generation of these interrupts by setting the...
Page 196: Addressing In Sisd And Simd Modes
DAG Operations instruction modifies addresses in any DAG index register MODIFY ) without accessing memory. If the register’s corresponding registers are set up for circular buffering, a instruction performs MODIFY the specified buffer wraparound (if needed). The syntax for is sim- MODIFY ilar to post-modify addressing (index, then modifier).
Page 197: Dags, Registers, And Memory
Data Address Generators DAGs, Registers, and Memory DAG registers are part of the DSP’s universal register ( ) set. Programs Ureg may load the DAG registers from memory, from another universal regis- ter, or with an immediate value. Programs may store DAG registers’ contents to memory or to another universal register.
Page 198 DAGs, Registers, and Memory DM OR PM DATA BUS 0X0000 0000 DAG1 OR DAG2 REGISTERS Figure 4-5. Normal Word (32-bit) DAG Register Memory Transfers The DAGs align extended-precision normal word (40-bit) addressed transfers or register-to-register transfers to bits 39-8 of the buses. These transfers between a 40-bit data register and 32-bit DAG1 or DAG2 regis- ters use the 64-bit DM and PM data buses.
Page 199: Dag Register Transfer Restrictions
Data Address Generators 64-bit bus, and the odd numbered register – 1 value ( in this example) transfers on the upper half (bits 63-32) of the bus. In both the even and odd numbered cases, the explicitly specified DAG register sources or sinks bits 31-0 of the long word addressed memory. DM OR PM DATA BUS IMPLICIT (NAMED + OR - 1) EXPLICIT (NAMED)
Page 200 DAGs, Registers, and Memory because the same bus is needed by both operations in the same cycle. Therefore, the second operation must be delayed. The following example causes a delay because it exhibits a write/read dependency in which written in one cycle. The results of that register write are not available to a register read for one cycle.
Page 201: Dag Instruction Summary
Data Address Generators DAG Instruction Summary Table 4-2, Table 4-3, Table 4-4, Table 4-5, Table 4-6, Table 4-7, Table 4-8, and Table 4-9 list the DAG instructions. For more information on assembly language syntax, see ADSP-21160 SHARC DSP Instruction Set Reference. In these tables, note the meaning of the following symbols: •...
Page 202 DAG Instruction Summary Table 4-2. Post-Modify Addressing, Modified by M Register and Updating I Register DM(I7–0,M7–0)=Ureg (LW); {DAG1} PM(I15–8,M15–8)=Ureg (LW); {DAG2} Ureg=DM(I7–0,M7–0) (LW); {DAG1} Ureg=PM(I15–8,M15–8) (LW); {DAG2} DM(I7–0,M7–0)=Data32; {DAG1} PM(I15–8,M15–8)=Data32; {DAG2} Table 4-3. Post-Modify Addressing, Modified by 6-bit Data and Updating I Register DM(I7–0,Data6)=Dreg;...
Page 203 Data Address Generators Table 4-5. Pre-Modify Addressing, Modified by 6-bit Data (No I Register Update) DM(Data6,I7–0)=Dreg; {DAG1} PM(Data6,I15–8)=Dreg; {DAG2} Dreg=DM(Data6,I7–0); {DAG1} Dreg=PM(Data6,I15–8); {DAG2} Table 4-6. Pre-Modify Addressing, Modified by 32-bit Data (No I Register Update) Ureg=DM(Data32,I7–0) (LW); {DAG1} Ureg=PM(Data32,I15–8) (LW); {DAG2} DM(Data32,I7–0)=Ureg (LW);...
Page 204 DAG Instruction Summary 4-26 ADSP-2126x SHARC Processor Hardware Reference...
Page 205: Memory
5 MEMORY The ADSP-2126x contains a large, dual-ported internal memory for single cycle, simultaneous, independent accesses by the core processor and I/O processor. The dual-ported memory, in combination with three separate on-chip buses, allow two data transfers from the core and one transfer from the I/O processor in a single cycle.
Page 206: Internal Memory
Internal Memory Internal Memory The ADSP-21262 and ADSP-21266 SHARC DSPs contain 2M bits of internal RAM and 4M bits of internal ROM. Block 0 has 1M bit RAM and 2M bits ROM. Block 1 has 1M bit RAM and 2M bits ROM. Table 5-1 shows the maximum number of data or instruction words that can fit in each internal memory block.
Page 207: Buses
Memory than the Von Neumann architecture provides, many DSPs use memory architectures that have separate data and address buses for program and data storage. These two sets of buses let the DSP retrieve a data word and an instruction simultaneously. This type of memory architecture is called Harvard architecture.
Page 208: Internal Address And Data Buses
Buses processor uses the I/O bus for memory accesses. The I/O processor’s par- allel port (PP) bus can access external memory devices. Internal Address and Data Buses Figure 5-1 on page 5-5 shows that the PM and DM buses have access to internal memory.
Page 209 Memory INTERNAL EXTERNAL (DSP) MEMORY (SYSTEM) MEMORY DATA DATA BLOCK 0 ADDRESS ADDRESS BLOCK 1 ADDRESS DATA ADDRESS DATA ANY TWO PATHS SIMULTANEOUSLY PARALLEL PORT ADDRESSES AND DATA FOLLOW PARALLEL PATHS PM ADDRESS BUS PM DATA BUS 24/16 PX BUS EXCHANGE REGISTER DM ADDRESS BUS DM DATA BUS IO ADDRESS BUS...
Page 210: Internal Data Bus Exchange
Buses Because the DSP’s internal memory is arranged in four 16-bit wide by 96K columns, memory is addressable in widths that are multiples of col- umns up to 64 bits: 1 column = 16-bit words 2 columns = 32-bit words 3 columns = 48- or 40-bit words 4 columns = 64-bit words For more information on the how the DSP works with memory words, see...
Page 211 Memory Figure 5-2 shows that during a transfer between and a data reg- ister ( ), the bus transfers the upper 32 bits of the register file and Dreg zero-fills the eight least significant bits (LSBs). Instruction Examples Combined PX Register PX = DM(0x80000)(LW);...
Page 212 Buses register-to-internal memory transfers over the DM or PM data bus are either 48-bit transfers for the combined or 32-bit transfers (on bits 31-0 of the bus) for Figure 5-5 shows these transfers. Instruction Examples PX = DM (0xC0000) (LW); PM(I7,M7) = PX1;...
Page 213 Memory All transfers between the register and data registers ( R0–R15 S0–S15 are 40-bit transfers. The most significant 40 bits are transferred as shown Figure 5-3 on page 5-7. Figure 5-5 shows the transfer size between and internal memory over the PM or DM data bus when using the long word ( ) option.
Page 214: Adsp-2126X Memory Map
ADSP-2126x Memory Map PX1 = R0; /* R0 32-bit explicit move to PX1, and S0 32-bit implicit move to PX2 */ PX = R0; /* R0 40-bit explicit move to PX, but no implicit move for S0 */ Instruction Example PX = USTAT1;...
Page 215 Memory The ADSP-2126x has two blocks of RAM that contain up to 1M bit of memory each, and two blocks of ROM that contain up to 2M bits of memory each. Each block is physically comprised of four 16-bit columns. “Wrapping”, as shown in Figure 5-8 on page 5-14, allows the memory to...
Page 216: Memory Organization And Word Size
ADSP-2126x Memory Map  Normal word address space is also used by the program sequencer to fetch 48-bit instructions. Note that a 48-bit fetch spans three columns that can lead to a different address range between instruc- tion fetches and data fetches (Figure 5-7).
Page 217: Placing 32-Bit Words And 48-Bit Words
Memory • 32-bit normal word data (2 columns) • 16-bit short word data (1 column)  Extended-precision normal word data is only accessible if the IMDWx bit is set in the register. It is left-justified within a three col- SYSCTL umn location, using bits 47–8 of the location.
Page 218: Mixing 32-Bit Words And 48-Bit Words
ADSP-2126x Memory Map Figure 5-8 shows the memory ranges for each data size in the DSP’s inter- nal memory. Transitioning from 48-bit to 32-bit data with zero empty locations: (48-bit word top address) 32-bit word 3 32-bit word 2 32-bit word 1 32-bit word 0 48-bit word top 48-bit word top-1...
Page 219 Memory 48-bit words. The three possible transition arrangements appear in Figure 5-8, Figure 5-9, and Figure 5-10. Transitioning from 48-bit to 32-bit data with one empty location: (48-bit word top address) 32-bit word 3 32-bit word 2 32-bit word 1 32-bit word 0 Empty 48-bit word top...
Page 220: Restrictions On Mixing 32-Bit Words And 48-Bit Words
ADSP-2126x Memory Map Restrictions on Mixing 32-Bit Words and 48-Bit Words There are some restrictions that stem from the memory column rotations for three-column data (48- or 40-bit words) and they relate to the way that three-column data can mix with four-column data (32-bit words) in memory.
Page 221: Example: Calculating A Starting Address For 32-Bit Addresses
Memory • B is the base normal word address of the internal memory block; if B = 0x80000 (Block 0) else B = 0xC0000 (Block 1) • m is the first 32-bit normal word address to use after the end of 48-bit words Example: Calculating a Starting Address for 32-Bit Addresses The last valid address is 0x82694.
Page 222: Internal Interrupt Vector Table
ADSP-2126x Memory Map Listing 5-3. 48-Bit Word Allocation n = TRUNC{4[(m - B) / 2] / 3]} + B where: • m is the first 32-bit normal word address after the end of 48-bit words (1m values falls in the valid normal word address space) •...
Page 223: Secondary Processor Element (Pey)
Memory using the Internal Memory Data Width ( ) bits in the regis- IMDWx SYSCTL ter. If a block’s bit is cleared (=0), normal word accesses to the block IMDWx access 32-bit data. If a block’s bit is set (=1), normal word accesses IMDWx to the block access 48-bit data.
Page 224: Broadcast Register Loads
ADSP-2126x Memory Map For information on complementary (implicit) registers in SIMD mode accesses, see “Secondary Processor Element (PEy)” on page 5-19. For more information on complementary (implicit) memory locations in SIMD mode accesses, see “Accessing Memory” on page 5-22. Broadcast Register Loads The DSP’s bits in the register control broadcast...
Page 225: Illegal I/O Processor Register Access
Memory Illegal I/O Processor Register Access The DSP monitors I/O processor register access when the Illegal I/O pro- cessor Register Access ( ) bit in the register is set (=1). If access IIRAE MODE2 to the IOP registers is detected, an Illegal Input Condition Detected ) interrupt occurs.
Page 226: Using Memory Access Status
Using Memory Access Status Using Memory Access Status As described in “Illegal I/O Processor Register Access” on page 5-21 “Unaligned 64-Bit Memory Access” on page 5-21, the DSP can provide illegal access information for long word or I/O register accesses. When these conditions occur, the DSP updates an illegal condition flag in a sticky status ( ) register.
Page 227: Access Word Size
Memory “Internal Memory Data Width” on page 5-18. While mixed accesses of 48-bit words and 16-, 32-, or 64-bit words at the same address are not allowed, mixed read/writes of 16-, 32-, and 64-bit words to the same address are allowed. For more information, see “Restrictions on Mixing 32-Bit Words and 48-Bit Words”...
Page 228 Accessing Memory When data is accessed using long word addressing, the data is always long word aligned on 64-bit boundaries in internal memory space. When data is accessed using normal word addressing and the mnemonic, the pro- gram should maintain this alignment by using an even normal word address (least significant bit of address = 0).
Page 229: Instruction And Extended-Precision Normal Word Accesses
Memory Table 5-3. Neighbor Registers for Long Word Accesses PEx Neighbor Registers PEy Neighbor Registers r0 and r1 s0 and s1 r2 and r3 s2 and s3 r4 and r5 s4 and s5 r6 and r7 s6 and s7 r8 and r9 s8 and s9 r10 and r11 s10 and s11...
Page 230: Normal Word (32-Bit) Accesses
Accessing Memory The DSP transfers the 40-bit data to internal memory as a 48-bit value, zero-filling the least significant 8 bits on stores and truncating these 8 bits on loads. The register file source or destination of such an access is a single 40-bit data register.
Page 231: Setting Data Access Modes
Memory Setting Data Access Modes registers control the operating mode of the SYSCTL MODE1 MODE2 DSP’s memory. These register are described in Appendix A, Registers Reference. SYSCTL Register Control Bits The following bits in the register control memory access modes: SYSCTL •...
Page 232: Sisd, Simd, And Broadcast Load Modes
Accessing Memory Mode 2 Register Control Bits The following bits in the register control memory access modes: MODE2 • Illegal IOP Register Access Enable. Bit 20 ( ) enables MODE2 IIRAE detection of IOP register access (if 1) or disables detection (if 0). •...
Page 233: Instruction Examples
Memory Instruction Examples R8 = DM (I4,M3), PM (I12,M13) = R0; /* Dual access */ R0 = DM (I5,M5); / * Single access */ For examples of data flow paths for single and dual-data transfers, see the following section, “Internal Memory Access Listings” on page 5-30.
Page 234: Internal Memory Access Listings
Internal Memory Access Listings  The operation of the shadow Write FIFO is fully transparent to the user. The logic takes automatic control about SIMD, LW or unaligned access types. Moreover it is able to handle sequential 32 to 40-bit data type access since the address may be the same. Internal Memory Access Listings The processor’s DM and PM buses support many combinations of regis- ter-to-memory data access options.
Page 235: Short Word Addressing Of Single-Data In Sisd Mode
Memory memory locations. For more information and examples, see ADSP-21160 DSP Instruction Set Reference. • Programs can use odd or even modify values (1, 2, 3, …) to step through a buffer in single- or dual-data, SISD or broadcast load mode regardless of the data word size (long word, extended-preci- sion normal word, normal word, or short word).
Page 236 Internal Memory Access Listings data bus. The processor drives the other short word lanes of the data buses with zeros. In SISD mode, the instruction accesses the registers to transfer data from memory. This instruction accesses , whose short word WORD X0 address has “00”...
Page 237 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1...
Page 238: Short Word Addressing Of Dual-Data In Sisd Mode
Internal Memory Access Listings Short Word Addressing of Dual-Data in SISD Mode Figure 5-12 shows the SISD, dual-data, short word addressed access mode. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The 16-bit values for short word accesses are transferred using the least significant short word lanes of the PM and DM data buses.
Page 239 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1...
Page 240: Short Word Addressing Of Single-Data In Simd Mode
Internal Memory Access Listings Short Word Addressing of Single-Data in SIMD Mode Figure 5-13 shows the SIMD, single-data, short word addressed access mode. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The explicitly addressed (named in the instruction) 16-bit value is transferred using the least significant short word lane of the PM or DM data bus.
Page 241 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1...
Page 242: Short Word Addressing Of Dual-Data In Simd Mode
Internal Memory Access Listings Short Word Addressing of Dual-Data in SIMD Mode Figure 5-14 shows the SIMD, dual-data, short word addressed access. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The explicitly addressed 16-bit values are transferred using the least significant short word lanes of the PM and DM data bus.
Page 243 Memory ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1...
Page 244: 32-Bit Normal Word Addressing Of Single-Data In Sisd Mode
Internal Memory Access Listings 32-Bit Normal Word Addressing of Single-Data in SISD Mode Figure 5-15 shows the SISD, single-data, 32-bit normal word addressed access mode. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The 32-bit value for the normal word access completes a transfer using the least significant normal word lane of the PM or DM data bus.
Page 245 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD X3 WORD X2...
Page 246: 32-Bit Normal Word Addressing Of Dual-Data In Sisd Mode
Internal Memory Access Listings 32-Bit Normal Word Addressing of Dual-Data in SISD Mode Figure 5-16 shows the SISD dual-data, 32-bit normal word addressed access mode. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The 32-bit values for normal word accesses transfer using the least significant normal word lanes of the PM and DM data buses.
Page 247 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD X3 WORD X2...
Page 248: 32-Bit Normal Word Addressing Of Single-Data In Simd Mode
Internal Memory Access Listings 32-Bit Normal Word Addressing of Single-Data in SIMD Mode Figure 5-17 shows the SIMD, single-data, normal word addressed access mode. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The explicitly addressed (named in the instruction) 32-bit value completes a transfer using the least significant normal word lane of the PM or DM data bus.
Page 249 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD X3 WORD X2...
Page 250: 32-Bit Normal Word Addressing Of Dual-Data In Simd Mode
Internal Memory Access Listings 32-Bit Normal Word Addressing of Dual-Data in SIMD Mode Figure 5-18 shows the SIMD, dual-data, 32-bit normal word addressed access mode. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The explicitly addressed (named in the instruction) 32-bit values are transferred using the least significant normal word lane of the PM or DM data bus.
Page 251 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD X3 WORD X2...
Page 252: Extended-Precision Normal Word Addressing Of Single-Data
Internal Memory Access Listings Extended-Precision Normal Word Addressing of Single-Data Figure 5-19 on page 5-49 displays a possible single-data, 40-bit extended-precision normal word addressed access. For extended-precision normal word addressing, the processor treats each data bus as a 40-bit extended-precision normal word lane. The 40-bit value for the extended-precision normal word access is transferred using the most sig- nificant 40 bits of the PM or DM data bus.
Page 253 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD X3 WORD Y3 WORD X2 WORD Y2 WORD X2 WORD X1 WORD Y2 WORD Y1...
Page 254: Extended-Precision Normal Word Addressing Of Dual-Data
Internal Memory Access Listings Extended-Precision Normal Word Addressing of Dual-Data Figure 5-20 shows the SISD, dual-data, 40-bit extended-precision normal word addressed access mode. For extended-precision normal word addressing, the processor treats each data bus as a 40-bit extended-preci- sion normal word lane. The 40-bit values for the extended-precision normal word accesses are transferred using the most significant 40 bits of the PM and DM data bus.
Page 255 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD X3 WORD X2 WORD Y3 WORD Y2 WORD Y2 WORD Y1 WORD X2 WORD X1...
Page 256: Long Word Addressing Of Single-Data
Internal Memory Access Listings Long Word Addressing of Single-Data Figure 5-21 displays one possible single-data, long word addressed access. For long word addressing, the processor treats each data bus as a 64-bit long word lane. The 64-bit value for the long word access completes a transfer using the full width of the PM or DM data bus.
Page 257 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y2 WORD X2 WORD Y1 WORD X1 WORD X0 WORD Y0 NO ACCESS LONG WORD ACCESS...
Page 258: Long Word Addressing Of Dual-Data
Internal Memory Access Listings Long Word Addressing of Dual-Data Figure 5-22 shows the SISD, dual-data, long word addressed access mode. For long word addressing, the processor treats each data bus as a 64-bit long word lane. The 64-bit values for the long word accesses completes a transfer using the full width of the PM or DM data bus.
Page 259 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y2 WORD X2 WORD X1 WORD Y1 WORD X0 WORD Y0 LONG WORD ACCESS LONG WORD ACCESS...
Page 260: Broadcast Load Access
Internal Memory Access Listings Broadcast Load Access Figure 5-33 through Figure 5-40 provide examples of broadcast load accesses for single and dual-data transfers. These read examples show that the broadcast load’s to register access from memory is a hybrid of the cor- responding non-broadcast SISD and SIMD mode accesses.
Page 261 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1...
Page 262 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4...
Page 263 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD X3 WORD X2...
Page 264 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2...
Page 265 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD X3 WORD Y3 WORD X2 WORD Y2 WORD Y2 WORD Y1 WORD X2 WORD X1...
Page 266 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD X3 WORD Y3 WORD X2 WORD Y2 WORD X2 WORD X1...
Page 267 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y2 WORD X2 WORD Y1 WORD X1 WORD X0 WORD Y0 NO ACCESS LONG WORD ACCESS...
Page 268 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y2 WORD X2 WORD X1 WORD Y1 WORD X0 WORD Y0...
Page 269: Mixed-Word Width Addressing Of Long Word With Short Word
Memory Mixed-Word Width Addressing of Long Word with Short Word The mixed mode requires a dual data access in all cases. Modes like SISD, SIMD and Broadcast in conjunction with the address types LW, NW-40, NW-32 and SW will result in many different mixed word width access types to use in parallel between the two memory blocks.
Page 270 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X2 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X1...
Page 271: Mixed-Word Width Addressing Of Long Word With Extended Word
Memory Mixed-Word Width Addressing of Long Word with Extended Word Figure 5-32 shows an example of a mixed-word width, dual-data, SISD mode access. This example shows how the processor transfers a long word access on the DM bus and transfers an extended-precision normal word access on the PM bus.
Page 272 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y3 WORD Y2 WORD X2 WORD Y2 WORD Y1 WORD X1...
Page 273 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1...
Page 274 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD X11 WORD X10 WORD X9 WORD X8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X7 WORD X6 WORD X5 WORD X4...
Page 275 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD X3 WORD X2...
Page 276 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y5 WORD Y4 WORD X5 WORD X4 WORD Y3 WORD Y2...
Page 277 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD X3 WORD Y3 WORD X2 WORD Y2 WORD Y2 WORD Y1 WORD X2 WORD X1...
Page 278 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD X3 WORD Y3 WORD X2 WORD Y2 WORD X2 WORD X1...
Page 279 Memory MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y2 WORD X2 WORD Y1 WORD X1 WORD X0 WORD Y0 NO ACCESS LONG WORD ACCESS...
Page 280 Internal Memory Access Listings MEMORY ANY BLOCK ANY OTHER BLOCK … … … … … … … … … … … … … … … … … … … … … … … … WORD Y2 WORD X2 WORD X1 WORD Y1 WORD X0 WORD Y0...
Page 281: Jtag Test Emulation Port
6 JTAG TEST EMULATION PORT In addition to boundary scan, the JTAG Test Emulation Port supports other functions including background telemetry channels, cycle counting with , user-configurable hardware support, breakpoints, and a reg- EMUCLK ister for viewing the revision ID. JTAG Test Access Port The emulator uses JTAG boundary scan logic for ADSP-2126x communi- cations and control.
Page 282: Boundary Scan
Boundary Scan A Boundary Scan Description language (BSDL) file for the ADSP-2126x is available on the Analog Devices Web site. Refer to the IEEE 1149.1 JTAG specification for detailed information on the JTAG interface. This chapter assumes a working knowledge of the JTAG specification.
Page 283 JTAG Test Emulation Port The ADSP-2126x emulation features halt the processor at a predefined point to examine the state of the processor, execute arbitrary code, restore the original state, and continue execution.  The ADSP-2126x emulation features are a superset of the ADSP-21160 DSP emulation features.
Page 284: Background Telemetry Channel (Btc)
Background Telemetry Channel (BTC) The breakpoint start/end registers are mapped into the IOP register space of the ADSP-2126x. The , and registers occupy the EMUN EMUCLK EMUCLK2 same address space as the ADSP-2106x DSP. These facilities are Ureg read-only by the ADSP-2126x core in normal operation. Background Telemetry Channel (BTC) Programmers can read and write data to a set of memory-mapped buffers ) that are accessible by the emulator while the core is...
Page 285: Restrictions
JTAG Test Emulation Port Restrictions If a breakpoint interrupt comes at a point when the program is coming out of an interrupt service routine (ISR) of a prior breakpoint, then in some cases the breakpoint status will not reflect that the second break- point interrupt has occurred.
Page 286: Instruction Register
JTAG Related Registers Instruction Register The Instruction register shifts an instruction into the processor. This instruction selects the performed test and/or the access of the test data reg- ister. The instruction register is 5 bits long with no parity bit. A value of 10000 binary is loaded (LSB nearest ) into the Instruction register whenever the TAP reset state is entered.
Page 287 BYPASS REGISTER INSTRUCTION REGISTER Figure 6-1. Serial Scan Path Other registers, reserved for use by Analog Devices, exist. However, this group of registers should not be accessed as they can cause damage to the part. ADSP-2126x SHARC Processor Hardware Reference...
Page 288: Enhanced Emulation Status (Eemustat) Register
JTAG Related Registers Enhanced Emulation Status (EEMUSTAT) Register register acts as the breakpoint Status register for the EEMUSTAT ADSP-2126x. This register is a memory-mapped IOP register. The pro- cessor core can access this register. For I/O breakpoints, this register has two status bits, one each for the two I/O buses ( When a breakpoint is hit, a user interrupt is generated.
Page 289: Built-In Self-Test Operation (Bist)
JTAG Test Emulation Port Built-In Self-Test Operation (BIST) No self-test functions are supported by the ADSP-2126x. EMUIDLE Instruction instruction places the DSP in the idle state and triggers an EMUIDLE emulator interrupt. This operation uses the instruction as a soft- EMUIDLE ware breakpoint.
Page 290 References • Bleeker, Harry, P. van den Eijnden, and F. de Jong. Boundary-Scan Test—A Practical Approach. Kluwer Academic Press, 1993. • Hewlett-Packard Co. HP Boundary-Scan Tutorial and BSDL Ref- erence Guide. (HP part# E1017-90001) 1992. 6-10 ADSP-2126x SHARC Processor Hardware Reference...
Page 291 7 I/O PROCESSOR In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to per- form data transfers. The ADSP-2126x contains an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data.
Page 292: General Procedure For Configuring Dma
General Procedure for Configuring DMA Each DMA is referred to as a channel, and each channel is configured independently. There are 22 channels of DMA available on the ADSP-2126x processor— one channel for the SPI interface, one channel for the parallel port inter- face, 12 channels via the serial ports, and eight channels for the input data port (IDP).
Page 293: Iop/Core Interaction Options
I/O Processor • Input data port (IDP) 4. Enable DMA by setting the applicable bits in the appropriate registers: • parallel port – PPDEN PPCTL • serial port – for chaining) in SDEN_x SCHEN_x SPCTLx • SPI – for chaining) in SPIDEN SPICHEN SPIDMAC...
Page 294 IOP/Core Interaction Options this is the bits of the register can become active IDP_DMAx_STAT DAI_STAT even if DMA, through some IDP channel, is not intended. The following are some other I/O processor interrupt attributes. • When an unchained (single block) DMA process reaches comple- tion (as the count decrements to zero) on any DMA channel, the I/O processor latches that DMA channel’s interrupt.
Page 295 I/O Processor A channel interrupt mask in the IMASK LIRPTL DAI_IRPTL_PRI , and registers determines whether a latched DAI_IRPTL_RE DAI_IRPTL_FE interrupt is to be serviced or not. When an interrupt is masked, it is latched but not serviced.  By clearing a channel’s bit during chained DMA, programs mask the DMA complete interrupt for a DMA process within a chained DMA sequence.
Page 296 IOP/Core Interaction Options Table 7-1. DMA Interrupt Vector Locations (Cont’d) Associated Register(s) Bits Vector Interrupt Data Buffer Address Name Channel LIRPTL 0x4C SP4I RXSP4B, TXSP4B IRPTL/IMASK 0x30 SPIHI RXSPI, TXSPI (high priority option) LIRPTL 0x74 SPILI (low priority option) LIRPTL 0x50 RXPP, TXPP IRPTL/IMASK...
Page 297: Polling/Status Driven I/O
I/O Processor Table 7-1. DMA Interrupt Vector Locations (Cont’d) Associated Register(s) Bits Vector Interrupt Data Buffer Address Name Channel IRPTL/IMASK 0x2C DAIHI IDP_FIF0 (high priority option) LIRPTL 0x5C DAILI (low priority option) IRPTL/IMASK 0x2C DAIHI IDP_FIF0 (high priority option) LIRPTL 0x5C DAILI (low priority option)
Page 298: Dma Controller Operation
• Figure A-73 on page A-169 lists all the bits in DAI_IRPTL_H • Figure A-74 on page A-170 lists all the bits in DAI_IRPTL_L The DMA controller in the ADSP-2126x maintains the status informa- tion of the channels in each of the peripherals registers, SPMCTLxy PPCTL , and...
Page 299 I/O Processor parameters to the index, modify, and count registers, then set the DMA enable bit to re-enable DMA. Chained DMA. Chained DMA sequences are a set of multiple DMA operations, each autoinitializing the next in line. To start a new DMA sequence after the current one is finished, the IOP automatically loads new index, modify, and count values from an internal memory location pointed to by that channel’s chain pointer (...
Page 300: Chaining Dma Processes
Once a program starts a DMA process, the process is influenced by two external controls—DMA channel priority and DMA chaining. For more information, see “Managing DMA Channel Priority” on page 7-18 “Chaining DMA Processes” below. Chaining DMA Processes The location of the DMA parameters for the next sequence comes from the chain pointer ( ) register.
Page 301 I/O Processor field = 0x0000) until some event occurs that loads the register with a nonzero value. Writing all zeros to the address field of the chain pointer register ( ) also disables chaining.  Chained DMA operations may only occur within the same chan- nel.
Page 302: Address Register
IOP/Core Interaction Options  bit only effects DMA channels that have chaining enabled. Also, interrupt requests enabled by the bit are maskable with register. IMASK Because the bit is not part of the memory address in the chain pointer register, programs must use care when writing and reading addresses to and from the register.
Page 303: Transfer Control Block Chain Loading (Tcb)
I/O Processor Transfer Control Block Chain Loading (TCB) During TCB chain loading, the I/O processor loads the DMA channel parameter registers with values retrieved from internal memory. The address in the chain pointer register points to the highest address of the TCB (containing the index parameter).
Page 304: Setting Up And Starting The Chain
IOP/Core Interaction Options cannot be interrupted by a higher priority channel. For a list of DMA channels in priority order, see Table 7-5 on page 7-28. Setting Up and Starting the Chain To set up and initiate a chain of DMA operations, use these steps: 1.
Page 305 I/O Processor The sequence for setting up and starting a chained DMA is outlined in the following steps and can also be seen in “Chained DMA Transfers” on page 10-48. 1. Configure the TCB associated with each DMA in the chain except for the first DMA in the chain.
Page 306: Inserting A Tcb In An Active Chain
IOP/Core Interaction Options Listing 7-1. Chain Assignment R0=0; dm(CPx)=R0; /* clear CPx register */ R2=(TCB1+3) & 0x7FFFF; /* init DMA control registers and load IIx address of next TCB and mask address */ R2=bset R2 by 19; /* set PCI bit */ dm(TCB2)=R2;...
Page 307: Setting Up Dma Channel Allocation And Priorities
I/O Processor 1. Enter chain insertion mode by setting = 1 and SCHEN_A SDEN_A in the channel’s DMA control register, . The DMA inter- SPCTL0 rupt indicates when the current DMA sequence has completed. 2. Copy the address currently held in the chain pointer register to the chain pointer position of the last TCB in the chain that is being inserted.
Page 308: Managing Dma Channel Priority
IOP/Core Interaction Options Managing DMA Channel Priority The default channel priority is: DMA channel 0 as highest priority and DMA channel 22 as lowest priority. Table 7-5 on page 7-28 lists the DMA channels in priority order. When a channel becomes the highest priority requester, the I/O processor services the channel’s request.
Page 309: Dma Bus Arbitration
I/O Processor The I/O processor determines which DMA channel has the highest prior- ity internal DMA request during every cycle between each data transfer. Processor core accesses of I/O processor registers and TCB chain loading (both of which occur after the IOD transfer) are subject to the same prior- itization scheme as the DMA channels.
Page 310 IOP/Core Interaction Options When none of the peripherals request bus access, the highest priority peripheral, for example, peripheral#0, is granted the bus. However, this does not change the currently assigned priorities to various peripherals. Within a peripheral group the priority is highest for the higher indexed peripheral (see Table 7-3).
Page 311: Setting Up Dma Parameter Registers
I/O Processor Table 7-3. DMA Channel Allocation and Parameter Register Assignments (Cont’d) Data Buffer Group IOP Address of Data Description Channel Buffers Number IDP_FIF0 0x24D0 DAI IPD Channel 4 IDP_FIF0 0x24D0 DAI IDP Channel 5 IDP_FIF0 0x24D0 DAI IDP Channel 6 IDP_FIF0 0x24D0 DAI IDP Channel 7...
Page 312 Setting Up DMA Parameter Registers Similarly, DMA transfers between internal memory and serial, IDP or SPI ports have DMA parameters. When the I/O processor performs DMA between internal memory and one of these ports, the program sets up the parameters, and the I/O uses the port instead of the external bus. The direction (receive or transmit) of the I/O port determines the direc- tion of data transfer.
Page 313: Data Buffer Registers
I/O Processor Data Buffer Registers The data buffer registers in Figure 7-3 on page 7-22 shows the data buffer registers for each port. These registers include: • Serial Port Receive Buffer ( ). These receive buffers for the RXSPx serial ports have two position FIFOs for receiving data when con- nected to another serial device.
Page 314: Port, Buffer, And Dma Control Registers
Setting Up DMA Parameter Registers Port, Buffer, and DMA Control Registers The Port, Buffer, and DMA Control Registers in Figure 7-3 shows the control registers for the ports and DMA channels. These registers include: • Parallel Port Control register ( ).
Page 315 I/O Processor • Chain Pointer registers ( ). Chain pointer registers CPSPx CPSPI hold the starting address of the TCB (parameter register values) for the next DMA operation on the corresponding channel. These reg- isters also control whether the I/O processor generates an interrupt when the current DMA process ends.
Page 316: Addressing
Setting Up DMA Parameter Registers Addressing Figure 7-4 shows a block diagram of the I/O processor’s address generator (DMA controller). Table 7-4 lists the parameter registers for each DMA channel. The parameter registers are uninitialized following a processor reset. The I/O processor generates addresses for DMA channels much the same way that the Data Address Generators (DAGs) generate addresses for data memory accesses.
Page 317 I/O Processor DMA ADDRESS GENERATOR (INTERNAL ADDRESSES) LOCAL BUS INTERNAL MEMORY MODIFIER INDEX (ADDRESS) ADDRESS POST-MODIFY DMA WORD COUNTER LOCAL BUS – 1 COUNT CHAIN POINTER WORKING REGISTER DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES) LOCAL BUS EXTERNAL EIPP EMPP ECPP MEMORY EXT.
Page 318 Setting Up DMA Parameter Registers  If the I/O processor modifies the index register past the maximum 19-bit value to indicate an address out of internal memory, the index wraps around to zero. With the offset for the ADSP-2126x processor, the wraparound address is 0x0008 0000. ...
Page 319 I/O Processor Table 7-5. DMA Channel Registers: Controls, Parameters and Buffers (Cont’d) Control Parameter Registers Buffer Registers Description Channel Registers Number SPCTL3 IISP3A, IMSP3A, RXSP3A, TXSP3A Serial Port 3A Data CSP3A, CPSP3A SPCTL3 IISP3B, IMSP3B, RXSP3B, TXSP3B Serial Port 3B Data CSP3B, CPSP3B SPCTL2 IISP2A, IMSP2A,...
Page 320: Setting Up Dma
Setting Up DMA Table 7-5. DMA Channel Registers: Controls, Parameters and Buffers (Cont’d) Control Parameter Registers Buffer Registers Description Channel Registers Number IDP_CTL IDP_DMA_I6, IDP_D- IDP_FIFO DAI IDP Channel 6 MA_M6, IDP_DMA_C6 IDP_CTL IDP_DMA_I7, IDP_D- IDP_FIFO DAI IDP Channel 7 MA_M7, IDP_DMA_C7 SPICTL IISPI, IMSPI, CSPI,...
Page 321 I/O Processor memory. If the parameters configure the channel to transmit, the I/O pro- cessor transfers a word automatically from the source memory to the channel’s buffer register. These transfers continue until the I/O processor transfers the selected number of words as determined by the count param- eter.
Page 322 Setting Up DMA 7-32 ADSP-2126x SHARC Processor Hardware Reference...
Page 323: Parallel Port
8 PARALLEL PORT The ADSP-2126x processor has a parallel port that allows bidirectional transfers between it and external parallel devices. Using the parallel port bus and control lines, the processor can interface to 8-bit or 16-bit wide external memory devices. The parallel port provides a DMA interface between internal and external memory and has the ability to support core driven data transfer modes.
Page 324 CORE ACCESS INTERNAL MEMORY RECEIVE REGISTER RXPP PPSI AD[ 15 -0] PARALLEL PORT TRANSMIT REGISTER TXPP PPSO IIPP IMPP PARALLEL PORT ICPP PPCTL CONTROLLER EIPP EMPP ECPP EXTERNAL ADDRESS Figure 8-1. Parallel Port Block Diagram ADSP-2126x SHARC Processor Hardware Reference...
Page 325: Parallel Port Pins
Parallel Port Parallel Port Pins This section describes the pins that the parallel port uses for its operation. For a complete list of pin descriptions and package pinouts, see the prod- uct-specific data sheet for your device. • Address/Data (AD15–0) pins. The ADSP-2126x processor pro- vides time multiplexed address/data pins that are used for providing both address and data information.
Page 326: Alternate Pin Functions
Parallel Port Pins external 16 bits of data during the second half of the cycle when the signal is asserted. pin is active high by default, but can be set active low via the bit (bit 13) in the Parallel Port Control ( ) register.
Page 327: Parallel Data Acquisition Port As Address Pins
Parallel Port Parallel Data Acquisition Port as Address Pins PDAP use of AD[15:0] pins. When bit 26 of the register is IDP_PP_CTL set, the Parallel Data Acquisition Port (PDAP) reads from the parallel port’s pins. When this bit is cleared, the PDAP reads data using AD0–15 DAI pins .
Page 328: Reading From An External Device Or Memory
Parallel Port Operation In a read cycle, the signals are inactive and is strobed. If the upper 16 bits of the external address have changed, this cycle is always pre- ceded by an cycle. In 8-bit mode, the lower 8 bits of the address, EA7–...
Page 329: Writing To An External Device Or Memory
Parallel Port The order of 8 to 32-bit data packing is shown in Table 8-1. The first byte received is [ ], second [ ] and so on. The 16- to 32-bit packing 15:8 scheme is shown in the third column of the table. ...
Page 330: Transfer Protocol
 Table 8-2 does not show cycles; it shows only the order of the data reads and writes. Table 8-2. Unpacking Sequence for 32-Bit Data Transfer AD7–0, 32-bit to 8-bit AD15–0, 32-bit to 16-bit (8-bit bus, LSW first) (16-bit bus, LSW first) First Word 1;...
Page 331: 8-Bit Mode
Parallel Port 8-Bit Mode cycle always precedes the first transfer of data after the parallel port is enabled. During cycles for 8-bit mode, the upper 16 bits of the external address ( ) are driven on the 16-bit parallel port bus (pins EA23–8 ).
Page 332 occurs in two cycles. In cycle one, the processor performs an cycle, driving the 16 bits of external address, , onto the 16-bit parallel EA15–0 port bus (pins ), allowing the external latch to hold this address. In AD15–0 the second cycle, the processor either drives or receives the 16 bits of external data ( ) through the 16-bit parallel port bus (pins ED15–0...
Page 333: Comparison Of 16-Bit And 8-Bit Sram Modes
Parallel Port Comparison of 16-Bit and 8-Bit SRAM Modes When considering whether to employ the 16- or 8-bit mode in a particu- lar design, a few key points should be considered. • The 8-bit mode provides a 24-bit address, and therefore can access 16M bytes of external memory.
Page 334: Parallel Port Interrupt
Parallel Port Interrupt twice as fast as the 8-bit port, as the overhead for cycles is zero. This is convenient when interfacing to high speed 16-bit FIFO-based devices, including A/D and D/A converters. • In situations where a majority of address accesses are non-sequen- tial and cross 256 byte boundaries, the overhead of the cycles in the 8-bit mode approaches 20%...
Page 335 Parallel Port access constraints (occurrence of cycles at page boundaries, duration of data cycles, and/or addition of hold time cycles). The maximum parallel port speed is 1/3 of the core. The relationship between core clock and parallel port speed is static. For a 200 MHz core clock, the parallel port runs at 66 MHz.
Page 336: 8-Bit Access
Parallel Port Throughput 8-Bit Access In 8-bit mode, the first data-access (whether a read or a write) always con- sists of one cycle followed by four data cycles. As long as the upper 16 bits of address do not change, each subsequent transfer consists of four data cycles.
Page 337: Conclusion
Parallel Port cycle is needed at the very start of the transfer. Subsequent words, essentially written to the same address, do not require any cycles, and every parallel port cycle may be a 16-bit data cycle. In this case, the throughput is nearly doubled (except for the very first cycle) to over 132M bytes per second.
Page 338: Parallel Port Dma Registers
Parallel Port Registers For DMA transfers only, the following registers must also be initialized: • “Parallel Port DMA Internal Word Count Register (ICPP)” on page A-112 • “Parallel Port DMA Start Internal Index Address Register (IIPP)” on page A-112 • “Parallel Port DMA Internal Modifier Address Register (IMPP)”...
Page 339: Parallel Port External Setup Registers
Parallel Port This 24-bit register contains the number of words in external memory to be transferred via DMA. Parallel Port External Setup Registers The following registers must be initialized for both core-driven and DMA-driven transfers. • Parallel Port DMA External Index Address ( ) register EIPP This 24-bit register contains the external memory byte address used...
Page 340: Dma Transfers
Using the Parallel Port over core driven transfers is that the core can continue executing code while sequential data is imported/exported in the background. Unlike the external port on previous SHARC processors, the ADSP-2126x core cannot directly access the external parallel bus. Instead, the core ini- tializes two registers to indicate the external address and address-modifier and then accesses data through intermediate registers.
Page 341 Parallel Port . For all four of these methods, the core uses the same basic steps PPTX to initiate the transfer. However, each method uses a different technique to complete it. The following steps provide the basic procedure for setting up and initiating a data transfer using the core.
Page 342: Known Duration Accesses
Using the Parallel Port external byte address indicated by . Subsequently, additional data is EIPP fetched only when the core reads (empties) RXPP The following are guidelines that programs must follow when the proces- sor core accesses parallel port registers. •...
Page 343 Parallel Port occurs on the external bus. For example, after the core reads the TXPP PPTX register, it will take some number N core-cycles for the PP to shift out that data to the memory. During that time, the core can go on doing other tasks.
Page 344: Status Driven Transfers (Polling)
Using the Parallel Port Status Driven Transfers (Polling) The second method that the core may use to manage parallel port transfers involves the status bits in register, specifically the Parallel Port Bus PPCTL Status ( ) bit. This bit reflects the status of the external address pins PPBS and is used to determine when it is safe to disable and modify AD0-AD15...
Page 345: Parallel Port Programming Examples
Parallel Port Generally, interrupts are the best choice for DMA-driven parallel port transfers rather than core-driven transfers. Parallel Port Programming Examples This section provides two programming examples written for the ADSP-21262 processor. The first, Listing 8-1, uses the parallel port to transfer a buffer to 16-bit external memory using DMA.
Page 346 Parallel Port Programming Examples .section/dm seg_dmda; .var source[8] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888; .global _main; .section/pm seg_pmco; _main: ustat3 = dm(PPCTL); /*disable parallel port*/ bit clr ustat3 PPEN|PPDEN; dm(PPCTL) = ustat3; /* initiate parallel port DMA registers*/ r0 = source;...
Page 347 Parallel Port /* initiate PP DMA*/ /*Enable Parallel Port and PP DMA in same cycle*/ ustat4 = dm(PPCTL); bit set ustat4 PPDEN|PPEN; dm(PPCTL) = ustat4; _main.end: jump(pc,0); Listing 8-2. Parallel Port Status Driven Core Transfer /* Register Definitions */ #define PPCTL 0x1800 #define TXPP 0x1808...
Page 348 Parallel Port Programming Examples 0x77777777, 0x88888888; /* Main code section */ .global _main; .section/pm seg_pmco; _main: i4 = source; m4 = 1; /* setup ppdma registers for core use */ r0 = 1; dm(EMPP) = r0; r0 = 0x1000000; dm(EIPP) = r0; /* For 8-bit external memory, the External count is four times the internal count */ r0 = LENGTH(source) * 4;...
Page 349 Parallel Port Listing 8-3. Calculated Duration Core Driven Access _main: /* Setup once========================================= ustat3 = PPDUR3 | PPTRAN | PPEN; /* ustat3 enables PP */ ustat4 = PPDUR3 | PPTRAN; /* ustat4 disables PP */ dm(PPCTL) = ustat4; /* initialize but disable PP */ /* NOTE: Internal DMA registers AND the EXTERNAL COUNT can be left uninitialized for Core-driven transfers (External count determined by bus width: 16bit = count of 2, 8-bit = count of 4,...
Page 350 Parallel Port Programming Examples dm(EIPP) = r1; dm(PPCTL)= ustat3; /* enable PP */ dm(TXPP) = r2; <-- write to PP FIFO */ /* -----14 core cycles (minimum) available while each word is being transmitted. Writing to PPCTL has a 2 cycle effect-latency, so the result of writing this register in the 14th cycle doesn't take effect until the 16th cycle - which is one cycle after the cycle completes----- */...
Page 351: Serial Ports
9 SERIAL PORTS The ADSP-2126x processors have up to six independent, synchronous serial ports (SPORTs) that provide an I/O interface to a wide variety of peripheral devices. Each serial port has its own set of control registers and data buffers. With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols and provide a glueless hardware interface to many industry-standard data converters and codecs.
Page 352 bidirectional functionality provides greater flexibility for serial communications. Further, two SPORTs can be combined to enable full-duplex, dual-stream communications. • All serial data signals have programmable receive and transmit functions and thus have one transmit and one receive data buffer register (double-buffer) and a bidirectional shift register associated with each serial data signal.
Page 353 Serial Ports telephony interfaces. In multichannel mode, SPORT0 and SPORT1 work as a pair, SPORT2 and SPORT3 work as a pair, and SPORT4 and SPORT5 work as a pair. See “SPORT Opera- tion Modes” on page 9-9. When programming the serial port channel (A or B) as a transmit- ter, only the corresponding transmit buffers TXSPxA TXSPxB...
Page 354 DM DATA BUS DM DATA BUS PM DATA BUS PM DATA BUS I/O DATA BUS I/O DATA BUS TXSPxA TXSPxB RXSPxB RXSPxA TRANSMIT DATA TRANSMIT DATA BUFFER RECEIVE DATA BUFFER RECEIVE DATA BUFFER BUFFER HARDWARE HARDWARE COMPANDING COMPANDING (COMPRESSION) (EXPANSION) SPORTS 0, 2 &...
Page 355: Serial Port Signals
Serial Ports Serial Port Signals Figure 9-2 shows all of the signals used in the serial ports. SIGNAL ROUTING SERIAL PO RT SPO RT SIGNALS UNIT (SRU) SPORT0_DA SPORT0 CHANNEL A DA TA (RX OR TX) SP ORT 0_DA_I O S PORT0_DA SPORT0_DB SPORT0 CHANNEL B DA TA (RX OR TX)
Page 356 Serial Port Signals Any 20 of these 24 signals can be mapped to Digital Audio Interface ) pins through the signal routing unit (SRU). For more informa- DAI_Px tion, see “Digital Audio Interface” in Chapter 12, Digital Audio Interface., Table A-34 on page A-117, and Table A-35 on page A-121.
Page 357 Serial Ports Figure 9-1 shows a block diagram of a serial port. Setting the SPTRAN enables the data buffer path, which, once activated, responds by shifting data in response to a frame sync at the rate of . An application SPORTx_CLK program must use the correct serial port data buffers, according to the value of...
Page 358 signal, synchronous to the receive clock. If framing SPORTx_DB SPORTx_CLK signals are used, the signal indicates the beginning of the serial SPORTx_FS word being received. When an entire word is shifted in on the primary A channel, the data is (optionally) expanded (SPORT1, 3, and 5 only), then automatically transferred to the buffer.
Page 359: Sport Operation Modes
Serial Ports SPORT Operation Modes Serial ports operate in four modes: • Standard DSP Serial mode, described in “Standard DSP Serial Mode” on page 9-11 • Left-justified Sample Pair mode, described in “Left-Justified Sam- ple Pair Mode” on page 9-14 •...
Page 360 register is unique in that the name and functionality of its bits SPCTLx changes depending on the operation mode selected. In each section that follows, the bit names associated with the operating modes are described. Table 9-1 provides values for each of the bits in the SPORT Serial Con- trol ( ) registers that must be set in order to configure each specific SPCTLx...
Page 361: Standard Dsp Serial Mode
Serial Ports Standard DSP Serial Mode The Standard DSP Serial mode lets programs configure serial ports for use by a variety of serial devices such as serial data converters and audio codecs. In order to connect to these devices, a variety of clocking, framing, and data formatting options are available.
Page 362: Frame Sync Options
SPORT Operation Modes Frame Sync Options A variety of framing options are available for the serial ports. For detailed descriptions of framing options, see “Frame Sync Options” on page 9-34. In this mode, these options are independent of clocking, data formatting, or other configurations.
Page 363: Data Transfers
Serial Ports bit controls the configuration of transmit versus receive opera- SPTRAN tions. Serial ports can transmit or receive a selectable word length, which is programmed by the bits in the register. See “Setting Word SLEN SPCTL Length (SLEN)” on page 9-15 for more details.
Page 364: Left-Justified Sample Pair Mode
SPORT Operation Modes register. See “Serial Port Control Registers (SPCTLx)” on page 9-50 more details. Depending on the setting, these bits reflect the status of either the SPTRAN data buffers. TXSPxy RXSPxy Left-Justified Sample Pair Mode Left-justified Sample Pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync.
Page 365: Setting The Internal Serial Clock And Frame Sync Rates
Serial Ports Each SPORT transmit or receive channel has a buffer enable, DMA enable, and chaining enable bits in its Control register. The SPCTLx signal is used as the transmit and/or receive word select signal. SPORTx_FS DMA-driven or interrupt-driven data transfers can also be selected using bits in the register.
Page 366: Enabling Sport Master Mode (Mstr)
SPORT Operation Modes To transmit or receive words continuously in Left-justified Sample Pair mode, load the register with the same value as . For example, FSDIV SLEN for 8-bit data words ( = 7), set = 7. SLEN FSDIV Enabling SPORT Master Mode (MSTR) The SPORTs transmit and receive channels can be configured for Master or Slave mode.
Page 367: Enabling Sport Dma (Sden)
Serial Ports Enabling SPORT DMA (SDEN) DMA can be enabled or disabled independently on any of the SPORT’s transmit and receive channels. For more information, see “Moving Data Between SPORTS and Internal Memory” on page 9-65. SDEN_A (=1) to enable DMA and set the channel in DMA-driven data SDEN_B transfer mode.
Page 368: I 2 S Mode
SPORT Operation Modes SPORTX_CLK SPORTx_FS/WS LEFT-JUSTI FIED SAMPLE LSB n-1 MSB n LSB n MSB n+1 PAIR MO DE DATA O R SPORTX_DA OR SPORTX_DB SAMPLE n-1 SAMPLE n SAMPLE n+1 Figure 9-3. Word Select Timing in Left-justified Sample Pair Mode 1 This figure illustrates only one possible combination of settings attainable in the Left-justified Sam- ple Pair mode.
Page 369 Serial Ports The I S bus transmits audio data and control signals over separate lines. The data line carries two multiplexed data channels—the left channel and the right channel. In I S mode, if both channels on a SPORT are set up to transmit, then SPORT transmit channels ( ) transmit TXSPxA...
Page 370: I 2 S Mode Control Bits
SPORT Operation Modes S Mode Control Bits Several bits in the Control register enable and configure I S mode SPCTLx operation: • Operation mode, Master mode enable ( OPMODE • Word length ( SLEN • SPORT enable ( SPEN_A SPEN_B For more information, see “Serial Port Registers”...
Page 371: Setting Word Length (Slen)
Serial Ports • DMA enable ( SDEN_A SDEN_B • DMA chaining enable ( SCHEN_A SCHEN_B Setting Word Length (SLEN) SPORTs handle data words containing 8 to 32 bits in I S Mode. Pro- grams need to set the bit length for transmitting and receiving data words. For details, see “Word Length”...
Page 372: Selecting Frame Sync Options (Difs)
SPORT Operation Modes To select the channel order, set the bit (= 1) to transmit or receive on FRFS the left channel first, or clear the bit (= 0) to transmit or receive on FRFS the right channel first. Selecting Frame Sync Options (DIFS) When using both SPORT channels ( ) as trans- SPORTx_DA...
Page 373: Interrupt-Driven Data Transfer Mode
Serial Ports transfer mode. Clear (=0) to disable DMA and set the SDEN_A SDEN_B channel in an interrupt-driven data transfer mode. Interrupt-Driven Data Transfer Mode Both the A and B channels share a common interrupt vector in the inter- rupt-driven data transfer mode, regardless of whether they are configured as a transmitter or receiver.
Page 374: Multichannel Operation
SPORT Operation Modes SPORTX_CLK SPORTX_FS/WS LEFT-JUSTIFI ED SAMPLE LSB n-1 MSB n LSB n MSB n+1 PAIR MODE DATA OR SPORTX_DA OR SPORTX_DB WORD n-1 WORD n WO RD n+1 RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL Figure 9-4. Word Select Timing in I S Mode Multichannel Operation The serial ports offer a multichannel mode of operation, which allows the...
Page 375 Serial Ports Although the six SPORTs are programmable for data direction in the standard mode of operation, their programmability is restricted for multi- channel operations. The following points summarize these limitations: 1. The primary A channels of SPORT1, 3, and 5 are capable of expansion only, and the primary A channels of SPORT0, 2, and 4 are capable of compression only.
Page 376: Frame Syncs In Multichannel Mode
SPORT Operation Modes WORD 0 WORD 1 WORD 2 SPORT1_CLK SPORT1_DA IGNORED SPORT1_DB IGNORED SPORT1_FS SPORT0_DA SPORT0_DB SPORT0_FS Figure 9-5. Multichannel Operation Frame Syncs in Multichannel Mode All receiving and transmitting devices in a multichannel system must have the same timing reference. The signal is used for this reference, SPORT1_FS indicating the start of a block (or frame) of multichannel data words.
Page 377: Active State Multichannel Receive Frame Sync Select
Serial Ports is used as a transmit data valid SPORT0_FS SPORT2_FS SPORT4_FS signal, which is active during transmission of an enabled word. Because the serial port’s signals are SPORT0_DA/B SPORT2_DA/B SPORT4_DA/B three-stated when the time slot is not active, the signal specifies if SPORT0_FS/SPORT2_FS/SPORT4_FS is being driven by the processor.
Page 378 SPORT Operation Modes • SPORT transmit/receive enable ( SDEN_A SDEN_B • Master mode enable ( MSTR  If the bits are set (=1) in the register, the MCEA MCEB SPMCTLxy bits in the register must be cleared (=0). SPEN_A SPEN_B SPCTL Control registers contain several bits that enable and config- SPCTLx...
Page 379: Receive Multichannel Frame Sync Source
Serial Ports The 4-bit field (bits 4-1) in the Multichannel Control registers , and ) specifies a delay between the frame SPMCTL01 SPMCTL23 SPMCTL45 sync pulse and the first data bit in multichannel mode. The value of the number of serial clock cycles of the delay. Multichannel frame delay allows the processor to work with different types of telephony interface devices.
Page 380: Channel Selection Registers
SPORT Operation Modes Bit 29 ( ). The Transmit Underflow SPCTL0 SPCTL2 SPCTL4 TUVF_A Status (sticky, read-only) bit indicates (if set, =1) if the multichannel signal (from internal or external source) occurred while the SPORTx_FS buffer was empty. The SPORTs transmit data whenever they detect a signal.
Page 381 Serial Ports Table 9-2. Multichannel Selection Registers (Cont’d) Register Names Function MR1CCS(0–3) Multichannel Receive Compand Select specifies which active receive MR3CCS(0–3) channels (out of 128 channels) are companded. MR5CCS(0–3) MT0CCS(0–3) Multichannel Transmit Compand Select specifies which active transmit MT2CCS(0–3) channels (out of 128 channels) are companded. MT4CCS(0–3) Each of the four Multichannel Enable and Compand Select registers are 32 bits in length.
Page 382: Sport Loopback
SPORT Operation Modes incoming time slot data, while SPORT0, 2, and 4 compress selected out- going time slot data. SPORT Loopback When the SPORT loopback bit, bit 12 is set in the SPMCTL01 , or control registers, the serial port is configured in an SPMCTL23 SPMCTL45 internal loopback connection as follows: SPORT0 and SPORT1 work as a...
Page 383: Clock Signal Options
Serial Ports and I S modes support internal loopback. In loopback, each SPORT can be configured as transmitter or receiver, and each one is capable of generating internal frame sync and clock. Any of the three paired SPORTs can be set up to transmit or receive, depending on their bit configurations.
Page 384: Frame Sync Options
Frame Sync Options Frame Sync Options Framing signals indicate the beginning of each serial word transfer. A vari- ety of framing options are available on the SPORTs. The SPORTx_FS signals are independent and are separately configured in the Control register. Framed Versus Unframed Frame Syncs The use of frame sync signals is optional in serial port communications.
Page 385: Internal Versus External Frame Syncs
Serial Ports SPORTX_CLK FRAMED DATA UNFRAMED DATA Figure 9-6. Framed Versus Unframed Data Internal Versus External Frame Syncs Both transmit and receive frame syncs can be generated internally or input from an external source. The bit of the Control register deter- SPCTLx mines the frame sync source.
Page 386: Active Low Versus Active High Frame Syncs
Frame Sync Options Active Low Versus Active High Frame Syncs Frame sync signals may be active high or active low (for example, inverted). The bit of the Control register determines the frame SPCTLx sync’s logic level. • When is cleared (=0), the corresponding frame sync signal is active high.
Page 387: Early Versus Late Frame Syncs
Serial Ports Early Versus Late Frame Syncs Frame sync signals can be early or late. Frame sync signals can occur during the first bit of each data word or during the serial clock cycle immediately preceding the first bit. The bit of the Control LAFS...
Page 388: Data-Independent Frame Sync
Frame Sync Options SPORTX_CLK LATE FRAME SYNC EARLY FRAME SYNC DATA Figure 9-7. Normal Versus Alternate Framing Data-Independent Frame Sync When transmitting data out of the SPORT ( = 1), the inter- SPTRAN nally-generated frame sync signal normally is output-only when the transmit buffer has data ready to transmit.
Page 389: Data Word Formats
Serial Ports When = 1 and = 1, the internally-generated transmit frame DIFS SPTRAN sync is output at its programmed interval regardless of whether new data is available in the transmit buffer. The processor generates the transmit signal at the frequency specified by the value loaded in the SPORTx_FS register.
Page 390: Data Packing And Unpacking
Data Word Formats Do not set the value to 0 or 1. Words smaller than 32 bits are SLEN right-justified in the receive and transmit buffers, residing in the least sig- nificant (LSB) bit positions. Although serial ports process word lengths of 3 to 32 bits, transmitting or receiving words smaller than 7 bits at one-quarter the full clock rate of the processor may cause incorrect operation when DMA chaining is enabled.
Page 391: Data Type
Serial Ports (unpacking) operations. Companding can be used when word packing or unpacking is being used. When serial port data packing is enabled, the transmit and receive inter- rupts are generated for the 32-bit packed words, not for each 16-bit word. ...
Page 392: Companding
Data Word Formats These formats are applied to serial data words loaded into the receive and transmit buffers. Transmit data words are not zero-filled or sign-extended, because only the significant bits are transmitted. Table 9-4. DTYPE and Data Formatting (Multichannel) DTYPE Data Formatting Right-justify, zero-fill unused MSBs...
Page 393 Serial Ports each SPORT. Companding is selected by the field of the DTYPE SPCTLx Control register.  Companding is supported on the A channel only. SPORTs 0, 2, and 4 primary channels are capable of compression, while SPORTs 1, 3, and 5 primary channels are capable of expansion. In Multichannel mode, when companding is enabled, the number of channels must be programmed via the bit in the...
Page 394: Sport Control Registers And Data Buffers
SPORT Control Registers and Data Buffers 4. Wait one cycle. A instruction can be used to cause this delay; if is not inserted, the processor core is paused for one cycle any- way. This allows the serial port companding hardware to reload the transmit buffer with the companded value.
Page 395 Serial Ports ADSP-21xxx DSP Development Software. All control and status bits in the SPORT registers are active high unless otherwise noted. Since the SPORT registers are memory-mapped, they cannot be written with data directly from memory. Instead, they must be written from (or read into) processor core registers, usually one of the general-purpose Uni- versal registers ( ) of the register file or one of the general-purpose...
Page 396 SPORT Control Registers and Data Buffers Table 9-5. SPORT Registers (Cont’d) Register Reset Description Address 0x409 MR3CS0 None SPORT3 Multichannel Receive Select 0 (Channel 31–0) 0x40A MR3CS1 None SPORT3 Multichannel Receive Select 1 (Channel 63–32) 0x40B MR3CS2 None SPORT3 Multichannel Receive Select 2 (Channel 95–64) 0x40C MR3CS3...
Page 397 Serial Ports Table 9-5. SPORT Registers (Cont’d) Register Reset Description Address 0x466 TXSP3B 0x0000 0000 SPORT3 Transmit Data Buffer; B channel data 0x467 RXSP3B 0x0000 0000 SPORT3 Receive Data Buffer; B channel data 0x800 SPCTL4 0x0000 0000 SPORT4 Serial Control Register 0x801 SPCTL5 0x0000 0000...
Page 398 SPORT Control Registers and Data Buffers Table 9-5. SPORT Registers (Cont’d) Register Reset Description Address 0x80F MT4CCS2 0x0000 0000 SPORT4 Multichannel Transmit Compand Select 2 (Channel 95–64) 0x810 MT4CCS3 0x0000 0000 SPORT4 Multichannel Transmit Compand Select 3 (Channel 127–96) 0x811 MR5CCS0 0x0000 0000 SPORT5 Multichannel Receive Compand Select...
Page 399 Serial Ports Table 9-5. SPORT Registers (Cont’d) Register Reset Description Address 0xC05 MT0CS0 0x0000 0000 SPORT0 Multichannel Transmit Select 0 (Channels 31–0) 0xC06 MT0CS1 0x0000 0000 SPORT0 Multichannel Transmit Select 1 (Channels 63–32) 0xC07 MT0CS2 0x0000 0000 SPORT0 Multichannel Transmit Select 2 (Channels 95–64) 0xC08 MT0CS3...
Page 400: Register Writes And Effect Latency
SPORT Control Registers and Data Buffers Table 9-5. SPORT Registers (Cont’d) Register Reset Description Address 0xC14 MR1CCS3 0x0000 0000 SPORT1 Multichannel Receive Compand select 3 (Channels 127–96) 0xC60 TXSP0A 0x0000 0000 SPORT0 Transmit Data Buffer; A channel data 0xC61 RXSP0A 0x0000 0000 SPORT0 Receive Data Buffer;...
Page 401 Serial Ports clear the Serial Port Control register before the new mode is written to the register. There is one Global Control and Status register for each paired SPORT (SPORT0/1, SPORT 2/3 and SPORT 4/5) for multichannel operation. These are , or .
Page 402 SPORT Control Registers and Data Buffers Table 9-6. SPCTLx Control Bit Comparison in Four SPORT Operation Modes (Cont’d) Multichannel Mode Transmit Control Bits Receive Control Standard DSP Left-justified and I (SPORT0, 2, Bits (SPORT1, 3, Serial Mode Sample Pair Mode and 4) and 5) CKRE...
Page 403 Serial Ports The following bits, listed in bit number order, control serial port modes and are part of the (transmit and receive) Control registers. Other SPCTLx bits in the registers set up DMA and I/O processor-related serial SPCTLx port features. For information about configuring a specific operation mode, refer to Table 9-1 on page 9-10 “Standard DSP Serial Mode”...
Page 404 SPORT Control Registers and Data Buffers This description applies only to DSP Standard Serial mode and Multi- channel modes only. Serial Word Endian Select. Bit 3 ( ). This bit selects little SPCTLx LSBF endian words (LSB first, if set, = 1) or big endian words (MSB first, if cleared, = 0).
Page 405 Serial Ports Clock Rising Edge Select. bit 12 ( ). This bit selects whether SPCTLx CKRE the serial port uses the rising edge (if set, = 1) or falling edge (if cleared, = 0) of the clock signal for sampling data and the frame sync. This bit applies to DSP Standard Serial and Multichannel modes only.
Page 406 SPORT Control Registers and Data Buffers Serial Port DMA Chaining Enable. bits 19 and 21 ( SPCTLx SCHEN_A ). These bits enable (if set, = 1) or disables (if cleared, = 0) serial SCHEN_B port’s channels A and B DMA chaining. Bits 19 and 21 apply to all oper- ating modes.
Page 407 Serial Ports • 1 = SPORT is configured to transmit on both channels A and B. In this configuration, the buffers are activated, TXSPxA TXSPxB while the Transmit Shift registers are controlled by SPORTx_CLK . The buffers are inactive. SPORTx_FS RXSPxA RXSPxB This bit applies to I...
Page 408 SPORT Control Registers and Data Buffers When the SPORT is configured as a receiver, these bits provide receive overflow status. As a receiver, it indicates when the channel has received new data while the buffer is full. New data overwrites existing data. RXS_A •...
Page 409 Serial Ports  This bit applies to Multichannel mode only. Data Buffer Status Channel A (read-only). SPCTL1 SPCTL3 SPCTL5 bits 31–30 ( ). These bits indicate the status of the channel’s receive RXS_A buffer contents as follows: 00 = buffer empty, 01 = reserved, 10 = buffer partially full, 11 = buffer full.
Page 410: Transmit And Receive Data Buffers
SPORT Control Registers and Data Buffers Transmit and Receive Data Buffers The transmit buffers ( TXSP0A TXSP0B TXSP1A TXSP1B TXSP2A TXSP2B ) are the 32-bit trans- TXSP3A TXSP3B TXSP4A TXSP4B TXSP5A, TXSP5B mit data buffers for SPORT0, SPORT1, SPORT2, SPORT3, SPORT4, and SPORT5 respectively.
Page 411 Serial Ports Overflow/Underflow status bits are set when an overflow or underflow occurs. In multichannel mode, the bits are redefined due ROVF_A TUVF_A to the fixed-directional functionality of the registers. When the SPCTLx registers are configured for Multichannel SPCTL1 SPCTL3 SPCTL5 mode, the Receive Overflow bit indicates when the A channel has...
Page 412: Clock And Frame Sync Frequencies (Div)
SPORT Control Registers and Data Buffers interrupt is masked if serial port DMA is enabled or if the corresponding bit in the register is set. LIRPTL If your program causes the core processor to attempt to read from an empty receive buffer or to write to a full transmit buffer, the access is delayed until the buffer is accessed by the external I/O device.
Page 413 Serial Ports bit field specifies how many times the processor’s internal CLKDIV clock ( ) is divided to generate the transmit and receive clocks. The CCLK frame sync ( ) is considered a receive frame sync if the data sig- SPORTx_FS nals are configured as receivers.
Page 414: Sport Interrupts
SPORT Control Registers and Data Buffers can initiate periodic transfers. The counting of serial clock cycles applies to internally- or externally-generated serial clocks. The formula for the number of cycles between frame sync pulses is: # of serial clocks between frame syncs = FSDIV + 1 Use the following equation to determine the value of , given the FSDIV...
Page 415: Moving Data Between Sports And Internal Memory
Serial Ports interrupt vector. The interrupts can be used to indicate the completion of the transfer of a block of serial data when the serial ports are configured for DMA. They can also be used to perform single word transfers. Refer to “Single Word Transfers”...
Page 416: Dma Block Transfers
Moving Data Between SPORTS and Internal Memory port DMA is not enabled, the SPORT generates an interrupt every time it receives or starts to transmit a data word. The processor’s on-chip DMA controller handles the DMA transfer, allowing the processor core to con- tinue running until the entire block of data is transmitted or received.
Page 417 Serial Ports Table 9-8. Serial Port DMA Channels Channel Data Buffer Description Priority RXSP1A/TXSP1A SPORT1 A data Highest RXSP1B/TXSP1B SPORT1 B data RXSP0A/TXSP0A SPORT0 A data RXSP0B/TXSP0B SPORT0 B data RXSP3A/TXSP3A SPORT3 A data RXSP3B/TXSP3B SPORT3 B data RXSP2A/TXSP2A SPORT2 A data RXSP2B/TXSP2B SPORT2 B data RXSP5A/TXSP5A...
Page 418: Setting Up Dma On Sport Channels
Moving Data Between SPORTS and Internal Memory = 1), the transmit and receive interrupts are generated for the 32-bit PACK packed words, not for each 16-bit word. The following sections present an overview of serial port DMA operations; additional details are covered in the“Memory”...
Page 419: Sport Dma Parameter Registers
Serial Ports Table 9-9. SPORT DMA Parameter Registers Register Width Description (Y = A or B, and x = 0 – 5) IISPxy 19 bits DMA channel; x index; start address for data buffer IMSPxy 16 bits DMA channel; x modify; address increment CSPxy 16 bits DMA channel;...
Page 420 Moving Data Between SPORTS and Internal Memory Modify register ( ) for setting up a data buffer in internal memory. IMSPxy It is necessary to initialize the Index register with the starting address of the data buffer. After it transfers each serial I/O word to (or from) the SPORT, the DMA controller adds the modify value to the Index register to generate the address for the next DMA transfer.
Page 421 Serial Ports Table 9-10. SPORT DMA Parameter Registers Addresses (Cont’d) Register Address DMA Channel SPORT Buffer CPSP1A 0xc4B RXSP1A or TXSP1A IISP1B 0xc4C RXSP1B or TXSP1B IMSP1B 0xc4D RXSP1B or TXSP1B CSP1B 0xc4E RXSP1B or TXSP1B CPSP1B 0xc4F RXSP1B or TXSP1B Reserved IISP2A 0x440...
Page 422 Moving Data Between SPORTS and Internal Memory Table 9-10. SPORT DMA Parameter Registers Addresses (Cont’d) Register Address DMA Channel SPORT Buffer CPSP4A 0x843 RXSP4A or TXSP4A IISP4B 0x844 RXSP4B or TXSP4B IMSP4B 0x845 RXSP4B or TXSP4B CSP4B 0x846 RXSP4B or TXSP4B CPSP4B 0x847 RXSP4B or TXSP4B...
Page 423: Sport Dma Chaining
Serial Ports were reading an empty buffer that is currently active. This locks up the core until the SPORT is reset. Therefore, set the Direction bit, the Serial Port Enable bit, and DMA Enable bits before initiating any operations on the SPORT data buffers. If the DSP operates on the inactive transmit or receive buffers while the SPORT is enabled, it can cause unpredictable results.
Page 424: Sport Programming Examples
SPORT Programming Examples To avoid hanging the processor core—check the buffer’s full/empty status when the core’s program reads a word from a serial port’s receive buffer or writes a word to its transmit buffer. This condition can also happen to an external device, for example a host processor, when it is reading or writing a serial port buffer.
Page 425 Serial Ports this example, drives the clock and frame sync, and the buffer will SPORT5 be transferred only one time. This section provides three programming examples written for the ADSP-21262 processor. The first listing, Listing 9-3, transmits a buffer of data from using direct core reads and writes and the SPORT2...
Page 426 SPORT Programming Examples /* Default Buffer Length */ #define BUFSIZE 10 .SECTION/DM seg_dmda; /* TX Buffers */ .var tx_buf1a[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; .var tx_buf1b[BUFSIZE] = 0x12345678, 0x23456789, 0x3456789A, 0x456789AB, 0x56789ABC, 0x6789ABCD, 0x789ABCDE, 0x89ABCDEF, 0x9ABCDEF0, 0xABCDEF01;...
Page 427 Serial Ports /* RX Transfer Control Blocks */ .var rx_tcb1[4] = 0,BUFSIZE,1,rx_buf0a; .var rx_tcb2[4] = 0,BUFSIZE,1,rx_buf0b; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: /* SPORT loopback: use SPORT0 as RX and SPORT1 as TX. For no loopback (TDM mode), program MTaCSb [a=0,2,4 & b=0,1,2,3] and MRcCSd [a=1,3,5 &...
Page 428 SPORT Programming Examples SCHEN_A| /* Enable Channel A DMA Chaining */ IFS| /* Internally-generated Frame Sync */ ICLK; /* Internally-generated Clock */ dm(SPCTL1) = ustat4; /* Configure SPORT0 as a receiver */ /* externally generating clock and frame sync */ r0 = 0x0;...
Page 429 Serial Ports /* Next TCB location for tx_tcb1 is tx_tcb2 */ /* Mask the first 19 bits of the TCB location */ r0 = (tx_tcb2 + 3) & 0x7FFFF; dm(tx_tcb1) = r0; /* Initialize SPORT DMA transfer by writing to the CP reg */ dm(CPSP1A) = r0;...
Page 430 SPORT Programming Examples #define BUFSIZE 10 .SECTION/DM seg_dmda; /* Transmit Buffer */ .var tx_buf2a[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; /* Receive Buffer */ .var rx_buf3a[BUFSIZE]; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: bit set mode1 CBUFEN;...
Page 431 Serial Ports i4 = tx_buf2a; m4 = 1; i12 = rx_buf3a; m12 = 1; SPORT_DMA_setup: /* set internal loopback bit for SPORT2 & SPORT3 */ bit set ustat3 SPL; dm(SPMCTL23) = ustat3; /* Configure SPORT2 as a transmitter */ /* internally generating clock and frame sync */ /* CLKDIV = [fCCLK(200MHz)/4 x FSCLK(20MHz)] –...
Page 432 SPORT Programming Examples r0 = dm(i4,m4); dm(TXSP2A) = r0; /* Receive data via SPORT3 and save via DAG2 */ r0 = dm(RXSP3A); pm(i12,m12) = r0; _main.end: jump (pc,0); Listing 9-3. SPORT Transmit Using DMA /* SPORT DMA Parameter Registers */ #define IISP4A 0x840 #define IISP5A...
Page 433 Serial Ports #define FSR 0x00002000 #define ICLK 0x00000400 /* Default Buffer Length */ #define BUFSIZE 10 .SECTION/DM seg_dmda; /*Transmit buffer*/ .var tx_buf5a[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; /*Receive buffer*/ .var rx_buf4a[BUFSIZE]; /* Main code section */ .global _main;...
Page 434 SPORT Programming Examples dm(SPCTL5) = r0; dm(SPMCTL45) = r0; SPORT_DMA_setup: /* SPORT 5 Internal DMA memory address */ r0 = tx_buf5a; dm(IISP5A) = r0; /* SPORT 5 Internal DMA memory access modifier r0 = 1; dm(IMSP5A) = r0; /* SPORT 5 Number of DMA transfers to be done */ r0 = @tx_buf5a;...
Page 435 Serial Ports dm(SPCTL5) = ustat4; /* Configure SPORT4 as a receiver */ /* externally generating clock and frame sync */ r0 = 0x0; dm(DIV4) = R0; ustat3 = SPEN_A| /* Enable Channel A */ SLEN32| /* 32-bit word length */ FSR| /* Frame Sync Required */ SDEN_A;...
Page 436 SPORT Programming Examples 9-86 ADSP-2126x SHARC Processor Hardware Reference...
Page 437: Serial Peripheral Interface Port
10 SERIAL PERIPHERAL INTERFACE PORT The ADSP-2126x processor is equipped with a synchronous serial periph- eral interface port that is compatible with the industry-standard Serial Peripheral Interface (SPI). The SPI port supports communication with a variety of peripheral devices including codecs, data converters, sample rate converters, S/PDIF or AES/EBU digital audio transmitters and receivers, LCDs, shift registers, microcontrollers, and FPGA devices with SPI emu- lation capabilities.
Page 438: Functional Description
Functional Description • Master or slave booting from a master SPI device • DMA capability to allow transfer of data without core overhead Functional Description The SPI interface contains a Transmit Shift ( ) and a Receive Shift TXSR ) register. The register serially transmits data and the regis- RXSR...
Page 439: Spi Interface Signals
Serial Peripheral Interface Port During data transfers one SPI device acts as the SPI master by controlling the data flow. It does this by generating the and asserting the SPI SPICLK Device Select signal ( ). The SPI master receives data using the SPIDS MISO pin and transmits using the...
Page 440: Spi Clock Signal (Spiclk)
SPI Interface Signals ports in a system that has multiple devices. Figure 10-2 shows the master-slave connections between two ADSP-2126x devices. ADSP-2126x ADSP-2126x SPI-COMPATIBLE MASTER DEVICE SPI-COMPATIBLE SLAVE DEVICE SPICLK SPICLK SPIDS FLAG N MOSI MOSI RXSR TXSR TXSPI RXSPI RXSPI TXSPI RXSR...
Page 441: Spiclk Timing
Serial Peripheral Interface Port signal is used to shift out the data driven onto the lines SPICLK MISO and shift in the data driven onto the lines. The data is always shifted MOSI out on one edge of the clock (referred to as the active edge) and sampled on the opposite edge of the clock (referred to as the sampling edge).
Page 442: Spi Device Select Signal
SPI Interface Signals requires these signals to be manually controlled in software via the SPIDSx bits in the register (the bits are ignored when =0). SPIFLG SPIDSx CPHASE SPI Device Select Signal signal is the Serial Peripheral Interface Device Select Input sig- SPIDS nal.
Page 443: Spi General Operations
Serial Peripheral Interface Port 8-bit host microcontroller is the SPI master. The processor can be booted via its SPI interface to allow application code and data to be downloaded prior to runtime. 8-bit Host ADSP-2126x SLAVE SPI DEVICE MICROCONTROLLER SCLK SPICLK S_SEL SPIDS...
Page 444: Spi Enable
is on a single node, and every pin should be connected. SPI trans- SPICLK mission and reception are always enabled simultaneously, unless the Broadcast mode has been selected. In Broadcast mode, several slaves can be configured to receive, but only one of the slaves can be in Transmit mode, driving the line.
Page 445: Master Mode Operation
Serial Peripheral Interface Port resistor is required on both the pins when this option is MOSI MISO selected. When the is set and the SPI port is configured as a master, the MOSI pin is three-stated when the data driven out on is logic-high.
Page 446: Slave Mode Operation
5. The SPI generates the programmed clock pulses on SPICLK simultaneously shifts data out of and shifts data in from MOSI MISO Before starting to shift, the Transmit Shift register is loaded with the contents of the register. At the end of the transfer, the TXSPI contents of the Receive Shift register are loaded into RXSPI...
Page 447: Multimaster Conditions
Serial Peripheral Interface Port If the transmit buffer remains empty, or the receive buffer remains full, the devices operate according to the states of the bits in the SENDZ register. SPICTL • If = 1 and the transmit buffer is empty, the device repeatedly SENDZ transmits zero’s on the pin.
Page 448: Spi Data Transfer Operations
SPI Data Transfer Operations SPI Data Transfer Operations The following sections provide information on the two methods the ADSP-2126x uses to transfer data; through the core or through DMA. Core Transmit and Receive Operations For core-driven SPI transfers, the software has to read from or write to the registers to control the transfer.
Page 449 Serial Peripheral Interface Port The SPI port supports both Master mode and Slave mode DMA. The fol- lowing sections describe Slave and Master mode DMA operation, DMA chaining, switching between transmit and receive DMA operations, and processing DMA interrupt errors. ...
Page 450: Master Mode Dma Operation
SPI Data Transfer Operations Master Mode DMA Operation To configure the SPI port for Master mode DMA transfers: 1. Specify which pin(s) to use as the slave-select signal(s) by set- ting one or more of the SPI Flag ( register) Select bits ( SPIFLG DSxEN bits 3–0).
Page 451 Serial Peripheral Interface Port When enabled as a master, the DMA engine transmits or receives data as follows: 1. If the SPI system is configured for transmitting, the DMA engine reads data from memory into the SPI DMA FIFO. Data from the DMA FIFO is loaded into the register and then into the TXSPI...
Page 452: Master Transfer Preparation
SPI Data Transfer Operations = 0, it repeatedly transmits the contents of the register. The SENDZ TXSPI underrun condition cannot generate an error interrupt in this mode. TUNF  For receive DMA in master mode the stops only when the SPICLK FIFO and buffer is full (even if the DMA count is zero).
Page 453: Slave Mode Dma Operation
Serial Peripheral Interface Port Table 10-1. Transfer Initiation (Cont’d) TIMOD Function Transfer Initiated Upon Action, Interrupt Transmit or Initiate new multiword If chaining is disabled, the SPI inter- Receive with transfer upon write to rupt is latched in the cycle when the DMA Enable bit.
Page 454: Slave Transfer Preparation
SPI Data Transfer Operations 3. Write to the register to enable the SPI DMA engine and SPIDMAC configure: • A receive access ( = 1) or SPIRCV • A transmit access ( = 0) SPIRCV If DMA chaining is desired, set the bit in the SPICHEN register.
Page 455 Serial Peripheral Interface Port • If = 0 and the DMA buffer is full, the incoming data is discarded, and the register is not updated. While per- RXSPI forming a receive DMA, the transmit buffer is assumed to be empty. If = 1, the device repeatedly transmits SENDZ zero’s on the...
Page 456: Changing Spi Configuration
SPI Data Transfer Operations Changing SPI Configuration Programs should take the following precautions when changing SPI configurations. • The SPI configuration must not be changed during a data transfer. • Change the clock polarity only when no slaves are selected. •...
Page 457: Switching From Transmit To Receive Dma
Serial Peripheral Interface Port 3. Disable the SPI Port by setting the bit, (bit 0) in the SPIEN SPICTL register, to zero. When performing transmit DMA transfers, data moves through a four deep SPI DMA FIFO, then into the buffer, and finally into the shift TXSPI register.
Page 458: Switching From Receive To Transmit Dma
SPI Data Transfer Operations 3. Clear all errors by writing to the W1C-type bits in the reg- SPISTAT ister. This ensures that no interrupts occur due to errors from a previous DMA operation. 4. Reconfigure the register and enable the SPI port. SPICTL 5.
Page 459 Serial Peripheral Interface Port With disabling of the SPI: 1. Write 0x00 to the register to disable SPI. Disabling SPI also SPICTL clears the register contents and the buffer status. RXSPI TXSPI 2. Disable DMA and clear the DMA FIFO by writing 0x80 to the register.
Page 460: Dma Error Interrupts
SPI Data Transfer Operations 4. Reconfigure the register to clear the registers. SPICTL TXSPI RXSPI 5. Configure DMA by writing to the DMA parameter registers and register using the bit (bit 0). These registers are SPIDMAC SPIDEN described in Table 7-4 on page 7-25.
Page 461: Dma Chaining
Serial Peripheral Interface Port Without disabling the SPI: 1. Disable DMA and clear the FIFO. For example, write 0x80 to the register. This ensures that any data from a previous DMA SPIDMAC operation clears before configuring a new DMA operation. 2.
Page 462: Spi Transfer Formats
SPI Transfer Formats Table 10-2. DMA Chaining Sequence Address Register Description CPSPI DMA Start Address Address in Memory CPSPI – 1 DMA Address Modifier Address increment CPSPI – 2 DMA Word Count Number of words to transfer CPSPI – 3 DMA Next TCB Pointer to address of next TCB SPI Transfer Formats...
Page 463 Serial Peripheral Interface Port format from the master may be changed between transfers to adjust to var- ious requirements of a slave device. When = 0, the slave select line, , must be inactive ( CPHASE SPIDS HIGH between each word in the transfer. When = 1, may either CPHASE...
Page 464: Beginning And Ending An Spi Transfer
SPI Transfer Formats CLO CK CYCLE NUMBER SPICLK CLKPL=0 SPICLK CLKPL=1 MOSI FROM MASTER MISO FROM SLAVE SPIDS TO SLAVE * = UNDEF INED Figure 10-7. SPI Transfer Protocol for CPHASE = 1 Beginning and Ending an SPI Transfer An SPI transfer’s defined start and end depend on the following: whether the device is configured as a master or a slave, whether the mode is CPHASE...
Page 465: Spi Word Lengths
Serial Peripheral Interface Port bit defines when the receive buffer can be read; the bit defines when the transmit buffer can be filled. The end of a single word transfer occurs when the bit is set. This indicates that a new word has just been received and latched into the receive buffer, .
Page 466: 8-Bit Word Lengths
SPI Word Lengths 8-Bit Word Lengths Eight-bit word lengths can be used when transmitting or receiving. When transmitting, the SPI port sends out only the lower eight bits of the word written to the SPI buffer. For example, if the processor executes the instructions below, the SPI port transmits 0x78 r0 = 0x12345678...
Page 467: 32-Bit Word Lengths
Serial Peripheral Interface Port For example, if the processor executes the following instructions, the SPI port transmits 0x5678 r0 = 0x12345678 dm(TXSPI) = r0; When receiving, the SPI port packs the 16-bit word to the lower 32 bits of buffer while the upper bits in the register are zeros. RXSPI For example, if an SPI host sends the processor the 32-bit word , the processor receives the following words:...
Page 468: Spi Interrupts
SPI Interrupts Transmitter packing example: The value (where is any random value and 0xXXLMXXJK the data words to be transmitted out of the SPI port) is written to the register. The processor transmits first and then transmits TXSPI 0xJK 0xLM Receiver packing example: The receiver unpacks the value and two words are received, and then...
Page 469 Serial Peripheral Interface Port During IOP-driven transfers (DMA), an SPI interrupt is triggered in these instances: 1. When a single DMA transfer completes 2. When a number of DMA sequences (if DMA chaining is enabled) completes 3. When a DMA error has occurred Again, the register must be initialized properly to enable DMA TIMOD...
Page 470: Spi Registers
SPI Registers • See the “Program Sequencer Registers” on page A-23 IRPTL register bit descriptions. LIRPTL • See “SPI DMA Configuration (SPIDMAC) Register” on page A-103 register bit descriptions. SPIDMAC SPI Registers The SPI peripheral in the ADSP-2126x SHARC processor includes several memory-mapped registers, some of which are accessible by the IOP.
Page 471 Serial Peripheral Interface Port Table 10-3 provides the bit descriptions for the register. SPIBAUD Table 10-3. SPIBAUD Register Bits Bit(s) Name Function Default Reserved 15:1 BAUDR Baud Rate enables the SPICLK baud rate per the following equation: SPI Baud Rate = Core clock (CCLK) divided by (4* BAUDR) 31:16 Reserved Table 10-4...
Page 472: Use Of Dsxen Bits In Spiflg For Multiple Slave Spi Systems
SPI Registers Use of DSxEN Bits in SPIFLG for Multiple Slave SPI Systems bits in the register are used in a multiple slave SPI envi- DSxEN SPIFLG ronment. For example, if there are five SPI devices in the system with an ADSP-2126x master, then the master ADSP-2126x processor can support the SPI mode transactions across all four other devices.
Page 473: Spi Device Select Input Pin
Serial Peripheral Interface Port SLAVE DEVICE SLAVE DEVICE SLAVE DEVICE SPIDS SPIDS SPIDS SPICLK SPICLK SPICLK MISO MOSI MISO MOSI MISO MOSI MISO MOSI SPIDS SPICLK FLAG FLAG FLAG MASTER DEVICE Figure 10-8. Single Master, Multiple Slave Configuration SPI Device Select Input Pin The behavior of the input depends on the configuration of the SPI.
Page 474: Spi Transmit Data Buffer Register (Txspi)
SPI Registers SPI Transmit Data Buffer Register (TXSPI) The Transmit Data Buffer register ( ) is a 32-bit read-write (RW) TXSPI register. Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the data in is loaded into TXSPI the Transmit Shift Data (...
Page 475: Spi Receive Data Buffer Register (Rxspi)
Serial Peripheral Interface Port SPI Receive Data Buffer Register (RXSPI) The Receive Data Buffer register ( ) is a 32-bit read-only (RO) regis- RXSPI ter that is accessible by both the software and DMA. At the end of a data transfer, the data in the Receive Shift register ( ) loads into the RXSR...
Page 476: Spi Dma Word Count Register (Cspi)
Error Signals and Flags SPI DMA Word Count Register (CSPI) This 16-bit register contains the number of DMA words to be transferred. When this register decrements from one to zero, the DMA is complete, and an interrupt may be triggered. ...
Page 477: Transmission Error Bit (Tunf)
Serial Peripheral Interface Port 3. The status bit in is set. SPISTAT 4. An SPI interrupt is generated. These four conditions persist until the bit is cleared by a write 1-to-clear (W1C-type) software operation. Until the bit is cleared, the SPI cannot be re-enabled, even as a slave.
Page 478: Reception Error Bit (Rovf)
Programming Model Reception Error Bit (ROVF) flag is set in the register when a new transfer has com- ROVF SPISTAT pleted before the previous data could be read from the register. This RXSPI bit indicates that a new word was received while the receive buffer was full.
Page 479: Master Mode Core Transfers
Serial Peripheral Interface Port Master Mode Core Transfers When the SPI is configured as a master, the SPI ports should be config- ured and transfers started using the following steps: 1. When is set to 0 with = 1, the slave-selects are auto- CPHASE CPHASE matically controlled by the SPI port.
Page 480: Slave Mode Core Transfers
Programming Model If the transmit buffer remains empty, or the receive buffer remains full, the device operates according to the states of the bits in the SENDZ registers. SPICTLx • If = 1 and the transmit buffer is empty, the device repeatedly SENDZ transmits zeros on the pin.
Page 481: Master Mode Dma Transfers
Serial Peripheral Interface Port 4. The reception or transmission continues until is released or SPIDS until the slave has received the proper number of clock cycles. 5. The slave device continues to receive or transmit with each new falling-edge transition on or active clock edge.
Page 482 Programming Model 3. Activate the desired slaves by clearing one or more of the SPI flag bits ( ) of the registers, if = 1. SPIFLGx SPIFLGx CPHASE 4. For a single DMA, define the parameters of the DMA transfer by writing to the , and registers.
Page 483: Slave Mode Dma Transfers
Serial Peripheral Interface Port service another DMA channel (or for another reason), the stalls SPICLK until data is written into the register. All aspects of SPI receive TXSPI operation should be ignored. The data in the register is not RXSPI intended to be used, and the (bits 28–27 and 31–30 in the SPICTLx...
Page 484: Chained Dma Transfers
Programming Model bytes may not be received by the SPI DMA due to the condition for gen- erating the DMA request. To configure for slave mode DMA: 1. Write to the register to make the mode of the serial link SPICTLx the same as the mode that is set up in the SPI master.
Page 485: Stopping Core Transfers
Serial Peripheral Interface Port 3. Write the first three parameters for the initial DMA to the IISPI , and registers directly. IMSPI CSPI IISPIB IMSPIB CSPIB 4. Select a baud rate using the register. SPIBAUD 5. Select which flag to use as the SPI slave select signal in the SPIFLG register.
Page 486: Stopping Dma Transfers
Programming Model Stopping DMA Transfers When performing transmit DMA transfers, data moves through a four deep SPI DMA FIFO, then into the buffers, and finally into the TXSPIx shift register. DMA interrupts are latched when the I/O processor moves the last word from memory to the peripheral. For the SPI, this means that the SPI “DMA complete”...
Page 487 Serial Peripheral Interface Port With disabled SPI: 1. Write 0x00 to the registers to disable SPI. Disabling the SPICTLx SPI also clears the registers and the buffer status. RXSPIx TXSPIx 2. Disable DMA by writing 0x00 to the register. SPIDMAxC 3.
Page 488: Switching From Receive To Receive/Transmit Dma
Programming Model Switching from Receive to Receive/Transmit DMA Use the following sequence to switch from receive to transmit DMA. Note that are registers but they may not contain any bits, TXSPIx RXSPIx only address information. With disabled SPI: 1. Write 0x00 to the registers to disable SPI.
Page 489: Dma Error Interrupts
Serial Peripheral Interface Port With enabled SPI: 1. Clear the registers and the buffer status without dis- RXSPIx TXSPIx abling the SPI by ORing 0xC0000 with the present value in the registers. Use the (bit 19) and (bit 18) bits SPICTLx RXFLSH TXFLSH...
Page 490 Programming Model With disabling the SPI: 1. Disable the SPI port by writing 0x00 to the registers. SPICTLx 2. Disable DMA and clear the FIFO by writing 0x80 to the SPIDMACx registers. This ensures that any data from a previous DMA opera- tion is cleared before configuring a new DMA operation.
Page 491: 11 Input Data Port
11 INPUT DATA PORT The signal routing unit (SRU) provides paths among both on-chip and off-chip peripherals. To make this feature effective in a real-world system, a low overhead method of making data from various serial formats parallel and routing them back to the main core memory is needed. The Input Data Port (IDP) provides this mechanism for a large number of asynchro- nous channels.
Page 492 PARALLEL DATA HANDLING PDAP HOLD Serial DATA Parallel SMODE0 Converter Serial DATA Parallel SMODE1 Converter Serial DATA Parallel SMODE2 Converter Serial DATA Parallel FIFO SMODE3 Converter IDP_FIFO (8 x 32) Serial DATA Parallel SMODE4 Converter Serial DATA Parallel SMODE5 Converter Serial DATA Parallel...
Page 493: Serial Inputs
Input Data Port Channels 0 through 7 can accept serial data in audio format. Channel 0 can also be configured to accept parallel data. The parallel input bypasses the serial-to-parallel converter and latches up to 20 bits per clock cycle. The parallel data is acquired through the Parallel Data Acquisition Port (PDAP) which provides a means of moving high bandwidth data to the core’s memory space.
Page 494 Serial Inputs protocol is designed to receive audio channels in I S, Left-justified Sample Pair, or Right-justified mode. One frame sync cycle indicates one 64-bit left-right pair, but data is sent to the FIFO as 32-bit words (that is, one-half a frame at a time). Contained within the 32-bit word is an audio signal that is normally 24 bits wide.
Page 495 Input Data Port Table 11-1. Serial Modes Bit Field Values Mode IDP_SMODEx Left-justified Sample Pair Reserved Reserved Right-justified Sample Pair 24 bits Right-justified Sample Pair 20 bits Right-justified Sample Pair 18 bits Right-justified Sample Pair 16 bits The polarity of left-right encoding is independent of the serial mode frame sync polarity selected in for that channel (Table...
Page 496: Parallel Data Acquisition Port (Pdap)
Parallel Data Acquisition Port (PDAP) SERIAL CLOCK IDPx_CLK_I FRAME SYNC (L/R) IDPx_FS_I LEFT-JUSTIFIED SAMPLE PAI R LSB n-1 MSB n LSB n MSB n SERIAL DATA IDPx_DAT_I FRAME [n-1] F RAME [n] FRAME [n] RIGHT RIGHT LEFT Figure 11-4. Timing in Left-justified Sample Pair Mode S ERIAL CLOCK IDPx_CLK_I FRAME SYNC (L/R)
Page 497 Input Data Port efficiency. The frame sync input is used to hold off latching of the next sample (that is, ignore the clock edges). The data then flows through the FIFO and is transferred by a dedicated DMA channel into the core’s memory as with any IDP channel.
Page 498: Masking
IDP_PORT_SELECT IDP_Pxx_MASK IDP_PP_PACKING IDP_PP_EN (IDP_PP_CTL[26]) (IDP_PP_CTL[19:0]) (IDP_PP_CTL[28:27]) (IDP_PP_CTL[31]) AD[15:0] [19:4] Packing DAI PINS MASK Unit [20:5] FIFO [3:0] DAI PINS [4:1] Serial Input Figure 11-6. Parallel Data Acquisition Port (PDAP) Functions Masking register provides 20 mask bits that allow the input IDP_PDAP_CTL from any of the 20 pins to be ignored.
Page 499: Packing Mode 11
Input Data Port MODE 11 1x20-bit RESERVED 12 11 MODE 10 2x16-bit 16 15 MODE 01 tri-word 21 20 10 9 MODE 00 4x8-bit 24 23 16 15 Figure 11-7. Packing Modes in IDP_PDAP_CTL Packing Mode 11 Mode 11 provides for 20 bits coming into the packing unit and 32 bits going out to the FIFO in a single cycle.
Page 500: Packing Mode 01
This mode sends one packed 32-bit word to FIFO for every two input clock cycles—the DMA transfer rate is one-half the PDAP input clock rate. Packing Mode 01 Mode 01 packs three acquired samples together. Since the resulting 32-bit word is not divisible by three, up to ten bits are acquired on the first clock edge and up to eleven bits are acquired on each of the second and third clock edges: •...
Page 501: Packing Mode 00
Input Data Port Clocking Edge Selection Notice that in all four packing modes described, data is read on a clock edge, but the specific edge used (rising or falling) is not indicated. Clock edge selection is configurable using the bit (bit 29 of IDP_PDAP_CLKEDGE register).
Page 502 Parallel Data Acquisition Port (PDAP) PDAP_CLK PDAP_DAT[19:12] PDAP_HOLD PDAP_CLK PDAP_DAT[19:12] PDAP_HOLD Figure 11-8. Hold Timing for Four 8-bit Words to 32 bits (Mode 00) 11-12 ADSP-2126x SHARC Processor Hardware Reference...
Page 503: Pdap Strobe
Input Data Port PDAP_CLK PDAP_DAT[19:4] PDAP_HOLD PDAP_CLK PDAP_DAT[19:4] PDAP_HOLD Figure 11-9. Hold Timing for Two 16-bit Words to 32 bits (Mode 10) PDAP Strobe Whenever the PDAP packing unit receives the number of sub words cor- responding to its select mode, it asserts the PDAP output strobe signal (all timing can be found the ADSP-2126x SHARC Processor Data Sheet).
Page 504: Fifo Control And Status
FIFO Control and Status FIFO Control and Status Several bits can be used to control and monitor FIFO operations: • IDP Enable. The bit (bit 7 of the register) IDP_ENABLE IDP_CTL enables the IDP. • IDP Buffer Hang Disable. The bit (bit 4 in the IDP_BHD IDP_CTL...
Page 505: Fifo To Memory Data Transfer
Input Data Port bit provides IDP FIFO overflow status information. IDP_FIFO_OVER This bit is set (= 1), whenever an overflow occurs. When this bit is cleared (= 0), it indicates there is no overflow condition. This read-only bit is a sticky bit, which does not automatically reset to 0 when it is no longer in overflow condition.
Page 506: Interrupt-Driven Transfers
FIFO to Memory Data Transfer • Eight dedicated DMA channels can sort and transfer the data into one buffer per source channel. When the memory buffer is full, the DMA channel raises an interrupt in the DAI Interrupt Controller. This method of moving data from the IDP FIFO is described in “DMA Transfers”...
Page 507 Input Data Port • bits in the register to spec- IDP_Pxx_PDAPMASK IDP_PDAP_CTL ify the input mask, if the PDAP is used. • bits in the register to spec- IDP_PORT_SELECT IDP_PDAP_CTL ify input from the DAI pins or the Parallel Port pins, if the PDAP is used.
Page 508: Interrupt-Driven Transfer Notes
FIFO to Memory Data Transfer Interrupt-Driven Transfer Notes The following items provide general information about interrupt driven transfers. • The three LSBs of FIFO data are the encoded channel number. These are transferred “as is” for this mode. These bits can be used by software to decode the source of data.
Page 509 Input Data Port 2. While the bits are , set the values IDP_DMA_EN IDP_ENABLE for the DMA parameter registers that correspond to channels 7–0. If some channels are not going to be used, then the corresponding parameter registers can be left in their default states: •...
Page 510: Dma Transfer Notes
FIFO to Memory Data Transfer 5. Connect all of the inputs to the IDP by writing to the SRU_DAT3 , and registers. SRU_DAT4 SRU_FS1 SRU_FS2 SRU_CLK1 SRU_CLK2 Keep the clock and frame sync of the ports connected to when data transfer is not intended. 6.
Page 511 Input Data Port • At the end of the DMA transfer for individual channels, interrupts are generated. These interrupts are generated after the last DMA data from a particular channel have been transferred to memory. These interrupts are mapped to the bit (bit 17), to IDP_DMA7_INT bit (bit 10) in the...
Page 512: Dma Channel Parameter Registers
FIFO to Memory Data Transfer  Note that when a DMA channel is not used (that is, parameter reg- isters are at their default values), that DMA channel’s corresponding bit is set (= 1). IDP_DMAx_STAT • The three LSBs of data from the serial inputs are channel encoding bits.
Page 513: Idp (Dai) Interrupt Service Routines For Dmas
Input Data Port IDP (DAI) Interrupt Service Routines for DMAs The IDP can trigger either the high priority DAI core interrupt reflected in the register or the low priority DAI core interrupt DAI_IRPTL_H reflected in the register. The ISR must read the correspond- DAI_IRPTL_L register to find all the interrupts DAI_IRPTL_H...
Page 514: Input Data Port Programming Example
Input Data Port Programming Example More than one DMA channel may have completed during this time period. For each, a bit is latched in the DAI_IRPTL_L registers. Ensure that the DMA registers are repro- DAI_IRPTL_H grammed. If any of the channels is not used, then its clock and frame sync must be held 5.
Page 515 Input Data Port Listing 11-1. Interrupt-Driven Data Transfer /* Using Interrupt-Driven Transfers from the IDP FIFO */ #define IDP_ENABLE /* IDP_ENABLE = IDP_CTL[7] */ #define IDP_CTL (0x24B0) /* Memory-mapped register */ #define IDP_FIFO_GTN_INT (8) /* Bit 8 in interrupt regs */ #define IDP_FIFO (0x24D0) /* IDP FIFO packing mode */...
Page 516 Input Data Port Programming Example (SRU_CLK1[19:15] = 01001) Connect IDP0_DAT_I to DAI_PB11_O (SRU_DAT3[11:6] = 001010) Connect IDP0_FS_I to DAI_PB12_O (SRU_FS1[19:15] = 01011) /******************************************************/ /* Pin buffers 10, 11 and 12 are always being used as */ /* inputs. Tie their enables to LOW (never driven). /******************************************************/ /* Connect PBEN10_I to LOW /* (SRU_PIN1[29:24] = 111110) */...
Page 517 Input Data Port r0 = dm(DAI_IRPTL_RE); /* Unmask for rising edge */ r0 = BSET r0 BY IDP_FIFO_GTN_INT; dm(DAI_IRPTL_RE) = r0; r0 = dm(DAI_IRPTL_FE); /* Mask for falling edge */ r0 = BCLR r0 BY IDP_FIFO_GTN_INT; dm(DAI_IRPTL_FE) = r0; r0 = dm(DAI_IRPTL_PRI); /* Map to high priority in core */ r0 = BSET r0 BY IDP_FIFO_GTN_INT;...
Page 518 Input Data Port Programming Example r0 = 0x000FFFFF; dm(DAI_PIN_PULLUP) = r0; /* pullup un-used DAI pins */ ustat2 = dm(IDP_CTL); /* Reset the IDP by enabling... */ bit set ustat2 IDP_EN; dm(IDP_CTL) = ustat2; bit clr ustat2 IDP_EN; /* ...and then disabling it */ dm(IDP_CTL) = ustat2;...
Page 519 Input Data Port IDP_P15_PDAPMASK| IDP_P14_PDAPMASK| IDP_P13_PDAPMASK| IDP_P12_PDAPMASK| IDP_P11_PDAPMASK| IDP_P10_PDAPMASK| IDP_P09_PDAPMASK| IDP_P08_PDAPMASK| IDP_P07_PDAPMASK| IDP_PDAP_CLKEDGE; /* latch data in falling edge of the clock that is provided to the PDAP dm(IDP_PP_CTL) = ustat2; ustat2 = IDP_DMA0_INT; dm(DAI_IRPTL_PRI)=ustat2; /* unmask individual interrupt for DMA_INT (PDAP) in RIC */ dm(DAI_IRPTL_RE)=ustat2;...
Page 520 Input Data Port Programming Example ustat2 = dm(IDP_PP_CTL); bit set ustat2 IDP_PDAP_EN; /* PDAP if set, IDP channel 0 if cleared ustat2 = dm(IDP_CTL); /* Start the IDP */ bit set ustat2 IDP_EN; dm(IDP_CTL) = ustat2; /* in packing mode 2, the data is stored in the buffer like this: 1|OOOOPPPP| 2|MMMMNNNN| 3|KKKKLLLL|...
Page 521 Input Data Port rts; IDP_ISR.end: ADSP-2126x SHARC Processor Hardware Reference 11-31...
Page 522 Input Data Port Programming Example 11-32 ADSP-2126x SHARC Processor Hardware Reference...
Page 523: 12 Digital Audio Interface
12 DIGITAL AUDIO INTERFACE The Digital Audio Interface (DAI) is comprised of a group of peripherals and the signal routing unit (SRU). The inputs and outputs of the periph- erals are not directly connected to external pins. Rather, the SRU connects the peripherals to a set of pins and to each other, based on a set of config- uration registers.
Page 524: Dai System Design
DAI System Design This virtual connectivity design offers a number of distinct advantages: • Flexibility • Increased numbers and kinds of configurations • Connections can be made via software—no hard-wiring is required  Inputs may only be connected to outputs. DAI System Design Figure Figure...
Page 525: Signal Routing Unit
Digital Audio Interface • Digital Audio Interface Pins. These pins provide the physical inter- face to the SRU. The DAI pins are described in “Pins Interface” on page 12-7. • Signal Routing Unit. The SRU provides the connection between the serial ports, IDP, and PCG and pins.
Page 526 Signal Routing Unit DAI PIN DAI PINS BUFFERS SIGNAL ROUTING UNIT DAI_PB11_O DAI_P11 DAI_PB11_I DAI_PB11_PE_I DAI_PB12_O DAI_P12 GENERAL-PURPOSE DAI_PB12_I COUNTER/TIMERS DAI_PB12_PE_I DAI_PB13_O TIMER1_O DAI_P13 DAI_PB13_I TIMER1_I DAI_PB13_PE_I TIMER2_O TIMER2_I DAI_PB14_O DAI_P14 DAI_PB14_I TIMER3_O DAI_PB14_PE_I TIMER3_I DAI_PB15_O DAI_P15 DAI_PB15_I DAI_PB15_PE_I SERIAL PORTS DAI_PB16_O DAI_P16...
Page 527 Digital Audio Interface DAI PIN DAI PINS BUFFERS SIGNAL ROUTING UNIT DAI_PB01_O DAI_P01 DAI_PB01_I PDAP_STRB_O DAI_PB01_PE_I PDAP DAI_PB02_O DAI_P02 DAI_PB02_I DMA0 IDP0 DAI_PB02_PE_I IDP0_DAT_I IDP0_FS_I IDP0_CLK_I DAI_PB03_O DAI_P03 DAI_PB03_I DAI_PB03_PE_I IDP1 IDP2 DAI_PB04_O IDP3 DAI_P04 DAI_PB04_I IDP4 DAI_PB04_PE_I IDP5 IDP6 IDP7 DAI_PB05_O DAI_P05...
Page 528 Signal Routing Unit compatible such that almost any output-to-input patch makes functional sense. SRU: GROUP A Inputs to peripherals in DAI (signal sinks) Outputs from peripherals in DAI (signal sources) Figure 12-3. Group A as a Patch Bay The SRU contains six groups that are named sequentially A through F. Each group routes a unique set of signals with a specific purpose.
Page 529: Pins Interface
Digital Audio Interface (for example, IDP channels). The mnemonic always ends with if the signal is an input, or with if the signal is an output. SIGNAL’S FUNCTION SPORT0_CLK_O PERIPHERAL DIRECTION RELATIVE TO SIGNAL’S PERIPHERAL Figure 12-4. Example SRU Mnemonic Note that it is not possible to connect a signal in one group directly to a signal in a different group (analogous to wiring from one patch bay to another).
Page 530 PBxx_O External PBxx_I PBxx_O Interface Package BUFFER to SRU Connection ENABLE PBENxx_I Figure 12-5. Pin Buffer Example The notation for pin input and output connections can be quite confusing at first because, in a typical system, a pin is simply a wire that connects to a device.
Page 531: Pin Buffers As Signal Output Pins
Digital Audio Interface PBxx_O EXTERNAL PBxx_O PBxx_I DRIVER INTERFACE PACKAGE TO SRU CONNECTION ENABLE PINENxx_I Figure 12-6. Input Signal from Off-chip Drives Pin Output when Pin is not Enabled While the pin is high impedance and another device is driving a logic level onto the external pin, this value is sent to the SRU as the pin interface output.
Page 532 dictated by the designated use of that pin. For example, if the DAI pin is hard-wired to only the input of another interconnected circuit, it would not make sense for the corresponding pin buffer to be configured as an input. Input pins are commonly tied to logic high or logic low to set the input to a fixed value.
Page 533: Pin Buffers As Signal Input Pins
Digital Audio Interface Pin Buffers as Signal Input Pins When the DAI pin is to be used only as an input, connect the correspond- ing pin buffer enable to logic low as shown in Figure 12-8. This disables the buffer amplifier and allows an off-chip source to drive the value pres- ent on the DAI pin and at the pin buffer output.
Page 534: Bidirectional Pin Buffers
Signal Routing Unit Bidirectional Pin Buffers All peripherals within the DAI that have bidirectional pins generate a cor- responding pin enable signal. Typically, the settings within a peripheral’s Control registers determine if a bidirectional pin is an input or an output, and is then is driven accordingly.
Page 535 Digital Audio Interface ). Note that the input and output signal pair are never SPORTx_CLK_PE_O used simultaneously. The pin enable signal dictates which of the two SPORT lines appears at the DAI pin at any given time. By connecting all three signals through the SRU, the standard SPORT configuration regis- ters behave as documented in “Serial Ports”...
Page 536 Signal Routing Unit PB01_O EXTERNAL PB01_O PACKAGE PB01_I CONNECTION ENABLE PBEN01_I PB02_O SPORT0_CLK_I SPORT0_CLK_O EXTERNAL PB02_O PACKAGE PB02_I SPORT0_CLK_PBEN_O CONNECTION ENABLE SPORT0_FS_I SPORT0_FS_O PBEN02_I SPORT0_FS_PBEN_O SPORT0_DA_I PB03_O SPORT0_DA_O SPORT0_DA_PBEN_O EXTERNAL PB03_O SPORT0_DB_I PACKAGE PB03_I CONNECTION SPORT0_DB_O ENABLE SPORT0_DB_PBEN_O PBEN03_I PB04_O EXTERNAL PB04_O PACKAGE...
Page 537: Making Connections In The Sru
Digital Audio Interface Making Connections in the SRU As described previously, the SRU is similar to a set of patch bays. Each bay routes a distinct set of outputs to compatible inputs. These connections are implemented as a set of memory-mapped registers with a bit field for each input.
Page 538 Making Connections in the SRU SRU: GROUP A SRU_CLK0 29:25 24:20 19:15 14:10 SPORT0_CLK_I SPORT5_CLK_I (10100) (11001) SPORT1_CLK_I SPORT4_CLK_I (10101) (11000) SPORT2_CLK_I SPORT3_CLK_I (10110) (10111) Figure 12-11. Patching to the Group A Register SRU_CLK0 Just as Group A routes clock signals, each of the other groups route a col- lection of compatible signals.
Page 539: Sru Connection Groups
Digital Audio Interface SRU Connection Groups The DAI/SRU has the default configuration shown in Table 12-1. Table 12-1. Default DAI/SRU Configuration (Pin Routing) Pin Number Signal Name Pin Type DAI_01 SDATA0A Three-State with programmable Pull-up DAI_02 SDATA0AB Three-State with programmable Pull-up DAI_03 SCLK0 Three-State with programmable Pull-up...
Page 540: Group A Connections - Clock Signals
Making Connections in the SRU Group A Connections – Clock Signals Group A is used to route signals to clock inputs. The SPORTs clock inputs (when the SPORTs are in clock slave mode), the clock inputs to the eight IDP channels and the two Precision Clock Generators (PCGs) external sources are selected from the list of Group A sources and set in the Group A registers.
Page 541: Group B Connections - Data Signals
Digital Audio Interface Group B Connections – Data Signals Group B connections, shown in Table 12-3, are used to route signals to serial data inputs. The serial data inputs to both the A and B channels of the SPORTs and to each of the eight IDP channels are selected from the list of Group B sources and set in the Group B registers.
Page 542: Group C Connections - Frame Sync Signals
Making Connections in the SRU Group C Connections – Frame Sync Signals Group C connections are used to route signals to frame sync inputs. The SPORT frame sync inputs (when the SPORT is in slave mode) and the frame sync inputs to the eight IDP channels are selected from the list of Group C sources and set in the Group C registers.
Page 543: Group D Connections - Pin Signal Assignments
Digital Audio Interface Group D Connections – Pin Signal Assignments Group D is used to specify any signals that will be driven off-chip by the pin buffers. A pin buffer input ( ) is driven as an output from DAI_PBxx_I the processor when the pin buffer enable is set (= 1).
Page 544 Making Connections in the SRU Table 12-5. Group D Sources – Pin Signal Assignments Signal Inputs Signal Sources DAI Pin Bit field Register • 20 External Pins (DAI_PBxx_O) SRU_PIN0 DAI_PB01_I • 12 Serial Port Data Channel Output Options (two DAI_PB02_I for each SPORT, and one for each Channel A/B) DAI_PB03_I (SPORTx_DB_O)
Page 545: Group E Connections - Miscellaneous Signals
Digital Audio Interface Group E Connections – Miscellaneous Signals Group E connections, shown in Table 12-6, are slightly different from the others in that the inputs and outputs being routed vary considerably in function. This group routes control signals (flags, timers, and so on) and provides a means of connecting signals between groups.
Page 546 Making Connections in the SRU Table 12-6. Group E Sources – Misc. Assignment Signal Inputs Signal Sources DAI Pin Register Bit field • 20 External Pins (DAI_PBxx_O) SRU_EXT_MISCA MISCA0_I • 3 Timers (TIMERx_O) DAI_INT_28 • 1 IDP Parallel Input Strobe Output FLG13_I (PDAP_STRB_O) MISCA1_I...
Page 547: Group F - Pin Enable Signals
Digital Audio Interface Group F – Pin Enable Signals Group F signals, shown in Table 12-7, are used to specify whether each DAI pin is used as an output or an input by setting the source for the pin buffer enables. When a pin buffer enable ( ) is set (= 1) the DAI_PBENxx_I signal present at the corresponding pin buffer input (...
Page 548: General-Purpose I/O (Gpio) And Flags
General-Purpose I/O (GPIO) and Flags General-Purpose I/O (GPIO) and Flags Any of the DAI pins may also be considered general-purpose input/output (GPIO) pins. Each of the DAI pins can also be set to drive a high or low logic level signal to assert signals. They can also be connected to miscella- neous signals and used as interrupt sources or as control inputs to other blocks.
Page 549 Digital Audio Interface “reads” of memory that do not exist. Catastrophic events are treated as high priority events. In comparison, normal interrupts are “determinis- tic”—specific events emanating from a source (the causes), the result of which is the generation of an interrupt. The expiration of a timer can gen- erate an interrupt, a signal that a serial port has received data that must be processed, a signal that an SPI has either transmitted or received data, and other software interrupts like the insertion of a trap that causes a break-...
Page 550: Dai Interrupts
DAI Interrupt Controller DAI Interrupts There are several registers in the DAI Interrupt Controller that can be configured to control how the DAI interrupts are reported to and serviced by the core’s Interrupt Controller. Among other options, each DAI inter- rupt can be mapped either as a high or low priority interrupt in the primary interrupt controller, certain DAI interrupts can be triggered on either the rising or falling edge of signals, and each DAI interrupt can also...
Page 551: High And Low Priority Latches
Digital Audio Interface High and Low Priority Latches In the ADSP-2126x, a pair of registers ( DAI_IRPTL_H DAI_IRPTL_L replace functions normally performed by the register. A single regis- IRPTL ter ( ) specifies the latch to which each of these interrupts DAI_IRPTL_PRI are mapped.
Page 552: Rising And Falling Edge Masks
DAI Interrupt Controller cleared. When the register is read, the low priority latched DAI_IRPTL_L interrupts are all cleared. Rising and Falling Edge Masks For interrupt sources that correspond to waveforms (as opposed to DAI event signals such as DMA complete or buffer full), the edge of a wave- form may be used as an interrupt source as well.
Page 553: Using The Sru() Macro
Digital Audio Interface Programs can manage responses to signals by configuring registers. In a sample audio application, for example, upon detection of a change of pro- tocol, the output can be muted. This change of output and the resulting behavior (causing the sound to be muted) results in an alert signal (an interrupt) being introduced in response (if the detection of a protocol change is a high priority interrupt).
Page 554 SRU(DAI_PB14_O,IDP3_FS_I); /* Connect pin buffer enable 19 to logic low */ SRU(LOW,PBEN19_I); Additional example code is available on the Analog Devices Web site.  There is a macro that has been created to connect peripherals used in a DAI configuration. This code can be used in both Assembly and C code.
Page 555: Precision Clock Generator
13 PRECISION CLOCK GENERATOR The Precision Clock Generator (PCG) consists of two units, each of which generates a pair of signals derived from a clock input signal. The pair of units, A and B, are identical in functionality and operate inde- pendently of each other.
Page 556 EXTERNAL OSCILLATOR OR XTAL CLKIN CORE CLOCK CORE BUFFER CORE CORE CLOCK GENERATOR PRECISION CLOCK SPORT GENERATOR SHARC ADSP-2126x EXTERNAL OSCILLATOR Figure 13-1. Clock Inputs Note that any clock and frame sync signals generated by the serial ports are also subject to these jitter problems because the SPORT clock is gener- ated from the core clock.
Page 557: Clock Outputs
Precision Clock Generator Clock Outputs As stated in the overview, each of the two units (A and B) produces a clock output and a frame sync output. The clock output is derived from the input to the PCG with a 20-bit divisor. Frequency of Clock Input Frequency of Clock Output = Clock Divisor...
Page 558: Frame Sync Outputs
Frame Sync Outputs than 50%. The low period of the output clock is one input clock period more than the high period of the output clock.  A PCG clock output cannot be fed to its own input. Setting SRU_- connects to logic low, not to CLK3[4:0] = 28...
Page 559: Frame Sync Output Synchronization With External Clock
Precision Clock Generator • Pulse width. A 16-bit value that determines the width of the fram- ing pulse. Settings for pulse width can be zero to . If the pulse DIV-1 width is equal to zero, then the actual pulse width of the output frame sync is: Frame Sync Divisor For even divisors:...
Page 560 Frame Sync Outputs through the (for PCGA) and (for PCGB) signals of the MISCA4_I MISCA5_I register. For more information, see “Miscellaneous SRU SRU_EXT_MISCA Registers (SRU_EXT_MISCx, Group E)” on page A-132. Synchronization with the external clock is enabled by setting bit 25 of the register for PCGA frame sync output and bit 10 of the SRU_CLK2 SRU_CLK3...
Page 561: Phase Shift
Precision Clock Generator respectively, these outputs are activated when a low to high transition is sensed in the external clock ( MISCA4_I MISCA5_I Phase Shift Another PCG frame sync parameter provides for phase shifting with respect to the clock of the same unit. This feature allows shifting in time relative to clock signals.
Page 562: Phase Shift Settings
Phase Shift Settings The phase shift between clock and frame sync outputs may be pro- grammed under these conditions: • The input clock source for the clock generator output and the frame sync generator output is the same. • Clock and frame sync are enabled at the same time using a single atomic instruction.
Page 563: Pulse Width
Precision Clock Generator CLOCK INPUT (FOR BO TH CLO CK AND FRAME SYNC) CLO CK OUTPUT FRAME SYNC OUTPUT (PHASE SHIFT = DIVISOR -1) FRAME SYNC OUTPUT (PHASE SHIFT = 0) FRAME SYNC OUTPUT (PHASE SHIFT = 1) FRAME SYNC OUTPUT (PHASE SHIFT = 2) ENABLE OTHER VALUES:...
Page 564: Bypass As A Pass Through
If the pulse width is equal to zero, then the actual pulse width of the frame sync output is equal to: DIVISOR if the divisor is even, or DIVISOR – 1 if the divisor is odd. Bypass Mode When the divisor for the frame sync has a value of zero or one, the frame sync is in Bypass mode, and the register has different functionality PCG_PW...
Page 565: Bypass As A One Shot
Precision Clock Generator CL OCK INPU T FO R FRAM E S Y NC FRAM E S YN C OUT PU T (INV FS A = 0, S TRO BEA = 0) FRAM E S YN C OUT PU T (INV FS A = 1, S TRO BEA = 0) Figure 13-4.
Page 566: Pcg Programming Examples
PCG Programming Examples CLOCK INPUT FOR FRAME SYNC MISCA2_I FRAME SYNC OUTPUT (INVFSA = 0, STROBEA = 1) FRAME SYNC OUTPUT (INVFSA = 1, STROBEA = 1) Figure 13-5. One Shot (Synchronous Clock Input and MISCA2_I) The second bit (bit 1) of the Pulse Width Control ( ) regis- INVFSA PCG_PW...
Page 567 Precision Clock Generator frame sync generated in this example is set for a 50% duty cycle, with no phase shift. Listing 13-1. PCG Channel B Output Example /* Register definitions */ #define SRU_CLK3 0x2434 #define SRU_PIN0 0x2460 #define SRU_PBEN0 0x2478 #define PCG_CTLB1 0x24C3 #define PCG_CTLB0...
Page 568 PCG Programming Examples /* Enable DAI Pins 1 & 2 as outputs */ r0 = PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02); dm(SRU_PBEN0) = r0; r0 = (100<<PCG_PWB); /* PCG Channel B FS Pulse width = 100 */ dm(PCG_PW) = r0; r2 = 1000; /* Define 20-bit Phase Shift */ r0 = (ENFSB|ENCLKB| /*Enable PCG Channel B Clock and FS*/ 1000000);...
Page 569 Precision Clock Generator #define SRU_PIN0 0x2460 #define SRU_PBEN0 0x2478 #define PCG_CTLA1 0x24C1 #define PCG_CTLA0 0x24C0 #define PCG_CTLB1 0x24C3 #define PCG_CTLB0 0x24C2 #define PCG_PW 0x24C4 /* SRU Definitions */ #define PCG_CLKA_O 0x1c #define PCG_CLKB_P 0x39 #define PCG_FSB_P 0x3B #define PBEN_HIGH_Of 0x01 //Bit Positions #define PCG_EXTB_I #define DAI_PB02...
Page 570 PCG Programming Examples /* Route PCG Channel B clock to DAI Pin 1 via SRU */ /* Route PCG Channel B frame sync to DAI Pin 2 via SRU */ r0 = (PCG_CLKB_P|(PCG_FSB_P<<DAI_PB02)); dm(SRU_PIN0) = r0; /* Enable DAI Pins 1 & 2 as outputs */ r0 = (PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02));...
Page 571: 14 Peripheral Timer
14 PERIPHERAL TIMER In addition to the internal core timer, the ADSP-2126x contains three identical 32-bit timers that can be used to interface with external devices. Each timer can be individually configured in any of three modes: • “Pulse Width Modulation Mode (PWM_OUT)” on page 14-7 •...
Page 572 Timer Architecture The timers also share one common status and control register, the Timer Global Status and Control ( ) register. TMSTAT For information on the Timer registers, see “Peripheral Timer Registers” on page A-157. I/O MEMORY DATA BUS PERIOD PULSE WIDTH –...
Page 573: Timer Status And Control
Peripheral Timer through the and the bits. Bit 31 is ignored for TMxPRD[30:0] TMxW[30:0] both. Assuming = 200 MHz: CCLK maximum period = 2 x (2 – 1) x 5 ns = 20 seconds. Timer Status and Control The Timer Global Status and Control ( ) register indicates the sta- TMSTAT tus of all three timers using a single read.
Page 574: Timer Interrupts
Timer Status and Control Table 14-1. Timer Global Status and Control (TMSTAT) Register Bits Bit(s) Name Definition TIM0IRQ Timer 0 Interrupt Latch Write one-to-clear (also an output) TIM1IRQ Timer 1 Interrupt Latch Write one-to-clear (also an output)1 TIM2IRQ Timer 2 Interrupt Latch Write one-to-clear (also an output)1 Reserved TIM0OVF Timer 0 Overflow/Error...
Page 575: Enabling A Timer
Peripheral Timer source without reference to the timer’s interrupt signal. The regis- TMSTAT ter contains an Interrupt Latch bit ( ) and an Overflow/Error TIMxIRQ Indicator bit ( ) for each timer. TIMxOVF The three timer interrupts are connected as follows: •...
Page 576 Enabling a Timer register. To enable all three timers in parallel, set all the TMSTAT TIMxEN bits in the register. TMSTAT Before enabling a timer, always program the corresponding timer’s Con- figuration ( ) register. This register defines the timer’s operating TMxCTL mode, the polarity of the signal, and the timer’s interrupt behav-...
Page 577: Pulse Width Modulation Mode (Pwm_Out)
Peripheral Timer Any of the timers can be used to implement a watchdog functionality that can be controlled by either an internal or an external clock source. For software to service the watchdog, the program must reset the timer value by disabling and then re-enabling the timer. Servicing the watchdog periodically prevents the Count register from reaching the period value and prevents the timer interrupt from being generated.
Page 578 Enabling a Timer • Width is equal to zero • Period value is lower than width value • Width is equal to period DATA BUS TMxW TMxPRD CLOCK TMxCNT RESET EQUAL? EQUAL? HIGH PWMOUT SET PWMOUT LOGIC INTERRUPT TMRX TIMER_ENABLE Figure 14-3.
Page 579: Pwm Waveform Generation
Peripheral Timer 0xFFFF FFFF – width. The timer counts upward to 0xFFFF FFF. Instead of incrementing to 0xFFFF FFFF, the timer then reloads the counter with the value derived from 0xFFFF FFFF – (period – width) and repeats. PWM Waveform Generation If the bit is set, the internally-clocked timer generates rectangular PRDCNT...
Page 580: Single-Pulse Generation
Enabling a Timer Single-Pulse Generation If the bit is cleared, the mode generates a single pulse on PRDCNT PWM_OUT signal. This mode can also be used to implement a well defined TIMERx software delay that is often required by state machines. The pulse width (= 2 x ) is defined by the width register and the period register is not TMxW...
Page 581 Peripheral Timer active low width pulse waveform is measured at the signal. The TIMERx internally-clocked timer is used to determine the period and pulse width of externally-applied rectangular waveforms. The Period and Width regis- ters are read-only in mode. The period and pulse width WDTH_CAP measurements are with respect to a clock frequency of CCLK...
Page 582 Enabling a Timer When the timer detects a first leading edge, it starts incrementing. When it detects the trailing edge of a waveform, the timer captures the current value of the Count register (= /2) and transfers it into the TMxCNT TMxW width registers.
Page 583: External Event Watchdog Mode (Ext_Clk)
Peripheral Timer The first width value captured in mode is erroneous due to syn- WDTH_CAP chronizer latency. To avoid this error, software must issue two instructions between setting mode and setting WDTH_CAP TIMxEN External Event Watchdog Mode (EXT_CLK) To enable mode, set the bits in the register to...
Page 584: Timer Programming Examples
Timer Programming Examples Timer Programming Examples This section provides three programming examples written for the ADSP-2126x. The first listing, Listing 14-1, sets up Timer 0 in External Watchdog mode, using DAI pin 1 as its input. The Timer generates an interrupt when it senses the number of edges are equal to the Timer Period setting.
Page 585 Peripheral Timer #define TIM0EN 0x00000100 /* Main code section */ .global _main; .section/pm seg_pmco; _main: /* Route Timer 0 Input to DAI Pin 1 via SRU */ r0 = (DAI_PB01_O<<TIMER0_I); dm(SRU_EXT_MISCB)=r0; ustat3 = TIMODEEXT| /* External Watchdog Mode */ PULSE| /* Positive edge is active */ IRQEN| /* Enable Timer 0 interrupt */...
Page 586 Timer Programming Examples #define TM0PRD (0x1403) /* GP Timer 0 Period register #define TM0W (0x1404) /* GP Timer 0 Width register #define TM1CTL (0x1409) /* GP Timer 1 Control register */ #define TM1CNT (0x140A) /* GP Timer 1 Count register #define TM1PRD (0x140B) /* GP Timer 1 Period register...
Page 587 Peripheral Timer /* Route Timer 0 Output to DAI Pin 1 via SRU */ r0 = TIMER0_Od;dm(SRU_PIN0) = r0; /* Enable DAI pin 1 as an output */ r0 = PBEN_HIGH_Of; dm(SRU_PBEN0) = r0; ustat3 = TIMODEPWM| /* PWM Out Mode */ PULSE| /* Positive edge is active */ PRDCNT;...
Page 588 Timer Programming Examples IRQEN| /* Enable Timer 1 Interrupt */ PRDCNT; /* Count to end of period */ dm(TM1CTL) = ustat3; R0 = TIM1EN; /* enable timer 1 */ dm(TMSTAT) = R0; /* Poll the Timer 1 interrupt latch, the interrupt will latch when the measured period and pulse width are ready to read */ bit tst LIRPTL GPTMR1I;...
Page 589 Peripheral Timer _main: /* Using PWM Out mode as a core timer */ ustat3 = TIMODEPWM| /* PWM Out Mode */ PRDCNT| /* Count to end of period */ IRQEN; dm(TM0CTL) = ustat3; R0 = 0x8000; dm(TM0PRD) = R0; /* Timer 0 period = 0x8000 */ R1 = 1;...
Page 590 Timer Programming Examples 14-20 ADSP-2126x SHARC Processor Hardware Reference...
Page 591: 15 System Design
15 SYSTEM DESIGN The processor supports many system design options. The options imple- mented in a system are influenced by cost, performance, and system requirements. This chapter provides the following system design information: • “Pin Descriptions” on page 15-2 • “Phase-Locked Loop Startup”...
Page 592: Pin Descriptions
Pin Descriptions Pin Descriptions The processor’s pin descriptions are fully described in the ADSP-2126x SHARC Processor Data Sheet. Pin Multiplexing The ADSP-2126x provides the same functionality as other SHARC pro- cessors but with a much lower pin count which helps to reduce total system costs.
Page 593 System Design Table 15-2. ADSP-2126x Processor Pin Multiplexing Scheme External Pin Function Type Control I = input 0 = cleared O = output 1 = set x = do not care FLGn PPFLGS = 0 FLGn SPIFLG[n] = 0 and SPIMS=0 IRQxEN = 0 PPFLGS=0 IRQn 2...
Page 594: Input Synchronization Delay
Pin Descriptions  If the system clock to the module is shut off in the SPICLK PMCTL register, are not usable. FLG0–3 Input Synchronization Delay The processor has several asynchronous inputs— , DAI RESET TRST IRQ2–0 pins and (when configured as inputs). These inputs can be FLG15-0 asserted in arbitrary phase to the processor clock, .
Page 595: Power Management Control Register
System Design On power-up, the pins are used to select ratios of 16:1, 8:1, CLKCFG1–0 and 3:1. After booting, numerous other ratios (slowing or speeding up the clock) can be selected via software control using the Power Management Control register. Power Management Control Register The ADSP-2126x has a Power Management Control register ( ) that...
Page 596 Pin Descriptions Listing 15-2. PMCTL Example Code. PLL Divisor modification: ustat2 = dm(PMCTL); bit set ustat2 DIVEN|PLLD8; /* set and enable PLL Divisor for CoreCLK = CLKIN/8 */ dm(PMCTL) = ustat2; PLL Multiplier modification: ustat2 = dm(PMCTL); bit set ustat2 PLLM8 | PLLBP; /* set a multiplier of 8 (default divisor is 2) and put PLL in Bypass */...
Page 597: Reset And Clkin
System Design r0 = 4096; /* wait for PLL to lock at new rate (requirement for modifying multiplier and setting INDIV bit only) */ lcntr = r0, do pllwait until lce; pllwait:nop; ustat2 = dm(PMCTL); bit clr ustat2 PLLBP; /* take PLL out of Bypass */ dm(PMCTL) = ustat2;...
Page 598 When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz. The internal clock generator, when used in conjunction with the pin and an external crystal, is designed to support up to a XTAL maximum of 25 MHz external crystal frequency. For all other external clock sources, the maximum frequency is 50 MHz.
Page 599: Reset Generators
The signal should not only offer a suitable RESET delay, but it should also have a clean monotonic edge. Analog Devices has a range of microprocessor supervisory ICs with different features. Features include one or more of the following: •...
Page 600 • Power low monitor • Backup battery switching The part number series for supervisory circuits from Analog Devices are: • ADM69x • ADM70x • ADM80x • ADM1232 • ADM181x • ADM869x A simple power-up reset circuit is shown below, using the ADM809-RART reset generator.
Page 601 System Design +1.2V DDINT +3.3V DDEXT 10µF V DDINT V DDEXT V CC RESET ADM809-RART ADSP-2126x Figure 15-1. Simple Reset Generator V DDEXT +3.3V 10µF V SENSE 100nF V DDEXT 100nF RESET ADM706TAR IRQ0 ADSP-2126x Vt=+1.25V IRQ1 FLAG0 RESET Figure 15-2. Reset Generator and Power Supply Monitor ADSP-2126x SHARC Processor Hardware Reference 15-11...
Page 602: Interrupt And Peripheral Timer Pins
Pin Descriptions Interrupt and Peripheral Timer Pins The processor’s external interrupt pins, flag pins, and timer pin can be used to send and receive control signals to and from other devices in the system. Hardware interrupt signals are received on the pins IRQ2–0 FLG2–0...
Page 603: Phase-Locked Loop Startup
A detailed discussion of JTAG and its use can be found in the Engi- neer-to-Engineer Note (EE-68), Analog Devices JTAG Emulation Technical Reference. This document is available on the Analog Devices Web site at www.analog.com. Phase-Locked Loop Startup...
Page 604: Conditioning Input Signals
Conditioning Input Signals counts up to 4096 cycles after is transitioned from low to CLKIN RESET high. The delay circuit is activated at the same time the PLL is taken out of reset. The advantage of the delayed core reset is that the PLL can be reset any number of times without having to power-down the system.
Page 605: Designing For High Frequency Operation
System Design reduce the effect of ringing on processor input signals with fast edges, because the amount of hysteresis that can be used on a CMOS chip is too small to make a difference. The small amount of hysteresis allowed is due to restrictions on the tolerance of the VIL and VIH TTL input levels under worst-case conditions.
Page 606: Other Recommendations And Suggestions
Designing for High Frequency Operation Jitter should be kept to an absolute minimum. High frequency jitter on the clock to the processor may result in abbreviated internal cycles. CLOCK FREQUENCY 1 ADSP-2126x Figure 15-5. Reducing Clock Jitter and Ring  Never share a clock buffer IC with a signal of a different clock fre- quency.
Page 607: Decoupling Capacitors And Ground Planes
System Design • Use 3.3 V peripheral components and power supplies to help reduce transmission line problems, ground bounce and noise cou- pling (the receiver switching voltage of 1.5 V is close to the middle of the voltage swing). • Experiment with the board and isolate crosstalk and noise issues from reflection issues.
Page 608: Recommended Reading
Designing for High Frequency Operation inches of ground lead causes ringing to be seen on the displayed trace and makes the signal appear to have excessive overshoot and undershoot. A 1 GHz or better sampling oscilloscope is needed to see the signals accurately.
Page 609: Booting
System Design circuit design. It is also an excellent source of information and practical ideas. Topics covered in the book include: • High-Speed Properties of Logic Gates • Measurement Techniques • Transmission Lines • Ground Planes and Layer Stacking • Terminations •...
Page 610 Booting The ADSP-2126x supports three booting modes—EPROM, SPI master and SPI slave. Each of these modes uses the following general procedure: 1. At reset, the ADSP-2126x is hardwired to load two hundred fifty-six 32-bit instruction words via a DMA starting at location 0x80000.
Page 611: Parallel Port Booting
System Design Table 15-6. Booting Modes BOOT_CFG1-0 Description SPI Slave boot SPI Master boot EPROM boot via parallel port ROM Boot mode (not available on all ADSP-2126x processors) Parallel Port Booting The ADSP-2126x supports an 8-bit boot mode through the parallel port. This mode is used to boot from external 8-bit wide memory devices.
Page 612: Spi Port Booting
Booting For a complete description of the Parallel Port Control register, see “Paral- lel Port Control Register (PPCTL)” on page A-108. The parallel port DMA channel is used when downloading the boot kernel information to the processor. At reset, the DMA Parameter registers are initialized to the values listed in Table 15-8.
Page 613 System Design to 32 bits. Therefore, for 8 or 16-bit devices, data words are packed into the Shift register to generate 32-bit words least significant bit (LSB) first, which are then shifted into internal memory. The relationship between the 32-bit words received into the register and the instructions that RXSPI need to be placed in internal memory is shown in...
Page 614: 32-Bit Spi Host Boot
Booting processor expects to receive instructions and data packed in a least signifi- cant word (LSW) format. Figure 15-8 shows how a pair of instructions are packed for SPI booting using a 32-, 16-, and an 8-bit device. These two instructions are received as three 32-bit words as illustrated in Figure 15-7.
Page 615: 16-Bit Spi Host Boot
System Design 0x90000 INTERNAL RXSPI MEMORY 0x900FF MOSI Figure 15-9. 32-Bit SPI Host Packing The 32-bit SPI host packs or prearranges the data as: SPI word 1= 0x33445566 SPI word 2 = 0xCCDD1122 SPI word 3 = 0x7788AABB 16-bit SPI Host Boot Figure 15-10 shows how a 16-bit SPI host packs 48-bit instructions at PM addresses 0x80000 and 0x80001.
Page 616: 8-Bit Spi Host Boot
Booting 0X80000 INTERNAL RXSPI MEMORY (LOADER KERNEL) 0X800FF MOSI Figure 15-10. 16-Bit SPI Host Packing The 16-bit SPI host packs or prearranges the data as: SPI word 1 = 0x5566SPI word 2 = 0x3344 SPI word 3 = 0x1122SPI word 4 = 0xCCDD SPI word 5 = 0xAABBSPI word 6 = 0x7788 The initial boot of the 256-word loader kernel requires a 16-bit host to transmit 768 16-bit words.
Page 617 System Design shifts to internal program memory during the load of the 256-instruction word kernel. The following example shows a 48-bit instructions executed. [0x80000] 0x112233445566 [0x80001] 0x7788AABBCCDD 0X80000 RXSPI INTERNAL MEMORY LOADER KERNEL 0X800FF MOSI Figure 15-11. 8-Bit SPI Host Packing The 8-bit SPI host packs or prearranges the data as: SPI word 1 = 0x66SPI word 2 = 0x55 SPI word 3 = 0x44SPI word 4 = 0x33...
Page 618: Slave Boot Mode
Booting SPI word 9 = 0xBBSPI word 10 = 0xAA SPI word 11 = 0x88SPI word 12 = 0x77 The initial boot of the 256-word loader kernel requires an 8-bit host to transmit fifteen hundred thirty-six 8-bit words. The SPI DMA count value of 0x180 is equal to 384 words.
Page 619 System Design Table 15-9. SPI Slave Boot Bit Settings Setting Comment SPIEN Set (= 1) SPI enabled SPIMS Cleared (= 0) Slave device MSBF Cleared (= 0) LSB first 10, 32-bit SPI Receive Shift register word length DMISO Set (= 1) MISO MISO disabled SENDZ Cleared (= 0)
Page 620: Master Boot
Booting Master Boot In Master Boot mode, the ADSP-2126x initiates the booting operation 1. Activating the signal and asserting the signal to the SPICLK FLG0 active low state. 2. Writing the read command 0x03 and address 0x00 to the slave device as shown in Figure 15-8.
Page 621 System Design The SPI DMA channel is used when downloading the boot kernel infor- mation to the processor. At reset, the DMA parameter registers are initialized to the values listed in Table 15-12. Table 15-12. Parameter Initialization Value for Master Boot Parameter Register Initialization Value Comment...
Page 622: Booting From An Spi Flash
Booting and VisualDSP++ have built-in support for creating a boot stream com- patible with both endian formats, and devices requiring 16-bit and 24-bit addresses, as well as those requiring no read command at all. Booting From an SPI Flash For SPI flash devices, the format of the boot stream will be identical to that used in SPI Slave mode, with the first byte of the boot stream being the first byte of the kernel.
Page 623 For convenience and consistency, Analog Devices provides a header file that provides these bit and registers definitions. CrossCore Embedded Studio provides proces- sor-specific header files in the directory.
Page 624 For convenience and consistency, Analog Devices provides a header file that contains these bit and registers definitions. CrossCore Embedded Studio provides proces- sor-specific header files in the directory.
Page 625: Registers Reference
Registers Reference Control and Status System Registers The DSP’s Control And Status System registers determine how the pro- cessor core operates and indicate the status of many processor core operations. In the SHARC Processor Programming Reference, these registers are referred to as System registers ( ), which are a subset of the DSP’s Sreg Universal registers (...
Page 626: Mode Control 1 Register (Mode1
Core Registers Mode Control 1 Register (MODE1) The mode control 1 register is a non memory-mapped, universal, system register ( Figure A-1 Table A-3 provide bit informa- Ureg Sreg tion for the register. MODE1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RND32 CBUFEN Rounding for 32-Bit Float-...
Page 627 Registers Reference Table A-2. Mode Control 1 Register (MODE1) Bit Descriptions Name Description Bit-Reverse Addressing For Index I8 Enable. Enables (bit reversed if set, = 1) or disables (normal if cleared, = 0) bit-reversed addressing for accesses that are indexed with DAG2 register I8. Bit-Reverse Addressing For Index I0 Enable.
Page 628 Core Registers Table A-2. Mode Control 1 Register (MODE1) Bit Descriptions (Cont’d) Name Description NESTM Nesting Multiple Interrupts Enable. Enables (nest if set, = 1) or dis- ables (no nesting if cleared, = 0) interrupt nesting in the interrupt controller. When interrupt nesting is disabled, a higher priority inter- rupt can not interrupt a lower priority interrupt’s service routine.
Page 629: Mode Control 2 Register (Mode2
Registers Reference Table A-2. Mode Control 1 Register (MODE1) Bit Descriptions (Cont’d) Name Description BDCST9 Broadcast Register Loads Indexed With I9 Enable. Enables (broad- cast I9 if set, = 1) or disables (no I9 broadcast if cleared, = 0) broad- cast register loads for loads that use the data address generator I9 index.
Page 630 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CAFRZ U64MAE Cache Freeze Unaligned 64-Bit Memory Access Enable IIRAE Illegal IOP Register Access Enable 15 14 13 12 11 10 EXTCADIS IRQ0E External Cache Interrupt Request Only Disable Sensitivity Select...
Page 631: Mode Mask Register (Mmask
Registers Reference Table A-3. Mode Control 2 Register (MODE2) Bit Descriptions (Cont’d) Name Description CADIS Cache Disable. This bit disables the instruction cache (if set, = 1) or enables the cache (if cleared, = 0). If this bit is set, then the caching of instructions from internal memory and external mem- ory both are disabled (see bit 6).
Page 632 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RND32 CBUFEN Rounding For 32-Bit Circular Buffer Addressing Enable Floating-Point Data Select BDCST1 PEYEN Broadcast Register Loads Processor Element Y Enable BDCST9 Broadcast Register Loads 15 14 13 12 11 10 TRUNC Truncation Rounding Mode...
Page 633: Arithmetic Status Registers (Astatx And Astaty)
Registers Reference Arithmetic Status Registers (ASTATx and ASTATy) registers are non memory-mapped, universal, sys- ASTATx ASTATy tem registers ( ). Each processing element has its own Ureg Sreg ASTAT register. The register indicates status for PEx operations, the ASTATx register indicates status for PEy operations. Figure A-4 ASTATy Table A-4...
Page 634 Core Registers Table A-4. ASTATx and ASTATy Register Bit Descriptions Name Description ALU Zero/Floating-Point Underflow. Indicates if the last ALU operation’s result was zero (if set, = 1) or non-zero (if cleared, = 0). The ALU updates AZ for all fixed-point and floating-point ALU operations. AZ can also indicate a floating-point underflow.
Page 635 Registers Reference Table A-4. ASTATx and ASTATy Register Bit Descriptions (Cont’d) Name Description ALU Floating-Point Invalid Operation. Indicates if the last ALU opera- tion’s input was invalid (if set, = 1) or valid (if cleared, = 0). The ALU updates AI for all fixed- and floating-point ALU operations. The processor sets AI and AIS in the STKYx/y register if the ALU operation: •...
Page 636 Core Registers Table A-4. ASTATx and ASTATy Register Bit Descriptions (Cont’d) Name Description Multiplier Floating-Point Underflow. Indicates if the last multiplier oper- ation’s result underflowed (if set, = 1) or did not underflow (if cleared, = 0). The multiplier updates MU for all fixed- and float- ing-point multiplier operations.
Page 637 Registers Reference Table A-4. ASTATx and ASTATy Register Bit Descriptions (Cont’d) Name Description Shifter Zero. Indicates if the last shifter operation’s result was zero (if set, = 1) or non-zero (if cleared, = 0). The shifter updates SZ for all shifter operations.
Page 638: Sticky Status Registers (Stkyx And Stkyy)
Core Registers Sticky Status Registers (STKYx and STKYy) These are non memory-mapped, universal, system registers ( Ureg ). Each processing element has its own register. The regis- Sreg STKY STKYx ter indicates status for PEx operations and some program sequencer stacks. register only indicates status for PEy operations.
Page 639 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CB7s LSEM DAG1 Circular Buffer 7 Loop Stack Empty (Read-only) Overflow LSOV CB15S Loop Stack Overflow (Read-only) DAG2 Circular Buffer 15 SSEM Overflow Status Stack Empty (Read-only) IIRA...
Page 640 Core Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Multiplier Floating-Point ALU Floating-Point Invalid Operation Underflow ALU Floating-Point Multiplier Floating-Point Underflow Overflow Multiplier Floating-Point Overflow ALU Fixed-Point Overflow Multiplier Fixed-Point Overflow...
Page 641 Registers Reference Table A-5. STKYx and STKYy Register Bit Descriptions (Cont’d) Description:  shows bits in both STKYx/y Name  shows bits in STKYx only  Multiplier Floating-Point Overflow. A sticky indicator for the multiplier MV bit. For more information, see “MV” on page A-13.
Page 642: Processing Element Registers
Core Registers Table A-5. STKYx and STKYy Register Bit Descriptions (Cont’d) Description:  shows bits in both STKYx/y Name  shows bits in STKYx only  SSEM Status Stack Empty. Indicates if the status stack is empty (if 1) or not empty (if 0)—not sticky, cleared by a Push.
Page 643: Data File Data Registers (Rx, Sx
Registers Reference Table A-6. Processing Element Registers Register Name and Page Reference Initialization After Reset “Data File Data Registers (Rx, Sx)” on page A-21 Undefined “PEx Multiplier Result Registers (MRFx, MRBx)” on page A-22 Undefined “Program Memory Bus Exchange Register (PX)” on page A-23 Undefined Data File Data Registers (Rx, Sx) The Data File Data registers are non memory-mapped, universal, data reg-...
Page 644: Pex Multiplier Result Registers (Mrfx, Mrbx
Core Registers PEx Multiplier Result Registers (MRFx, MRBx) registers are non memory-mapped. The PEx unit has a MRFx MRBx primary or foreground ( ) register and alternate or background ( results register. Fixed-point operations place 80-bit results in the multi- plier’s foreground register or background register, depending on...
Page 645: Pey Multiplier Result Registers (Msfx, Msbx
Registers Reference PEy Multiplier Result Registers (MSFx, MSBx) The MSFx and MSBx registers are non memory-mapped. The PEy unit has a primary or foreground (MSF) register and alternate or background (MSB) results register. Fixed-point operations place 80-bit results in the multiplier’s foreground MSF register or background MSB register, depending on which is active.
Page 646 Core Registers Table A-7. Program Sequencer Registers Register Initialization After Reset “Interrupt Latch Register (IRPTL)” on page A-25 0x0000 0000 (cleared) “Interrupt Mask Register (IMASK)” on page A-25 0x0000 0003 “Interrupt Mask Pointer Register (IMASKP)” on page A-26 0x0000 0000 (cleared) “Interrupt Register (LIRPTL)”...
Page 647: Interrupt Mask Register (Imask
Registers Reference Interrupt Latch Register (IRPTL) register is a non-memory-mapped, universal, system register IRPTL ). The register indicates latch status for interrupts. Ureg Sreg IRPTL Figure A-8 Table A-9 provide bit definitions for the register. IRPTL The programmable interrupt latch bits ( ) are con- P0I–P5I P14I–P16I...
Page 648: Interrupt Mask Pointer Register (Imaskp)
Core Registers Interrupt Mask Pointer Register (IMASKP) register is a non-memory-mapped, universal, system register IMASKP ). Each bit in the register corresponds to a bit with Ureg Sreg IMASKP the same name in the registers. The register field descrip- IRPTL IMASKP tions are shown in Figure...
Page 649 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SFT3I User Software Interrupt 3 Programmable Interrupt 5 SFT2I P14I User Software Interrupt 2 Programmable Interrupt 14 (DPI) SFT1I P15I User Software Interrupt 1 Programmable Interrupt 15 SFT0I P16I...
Page 650 Core Registers Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions Name Definition EMUI Emulator Interrupt. An EMUI occurs when the external emulator triggers an interrupt or the core hits a emulator breakpoint. Note this interrupt has highest priority, it is read-only and non-mas- kable RSTI Reset Interrupt.
Page 651 Registers Reference Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions (Cont’d) Name Definition Programmable Interrupt 0. A P0I interrupt occurs when the default/programmed peripheral sets (= 1) this bit. Programmable Interrupt 1. See P0I Programmable Interrupt 2. See P0I Programmable Interrupt 3. See P0I Programmable Interrupt 4.
Page 652: Interrupt Register (Lirptl)
Core Registers Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions (Cont’d) Name Definition SFT0I User Software Interrupt 0. An SFT0I occurs when a program sets (= 1) this bit. SFT1I User Software Interrupt 1. See SFT01. SFT2I User Software Interrupt 2. See SFT01. SFT3I User Software Interrupt 3.
Page 653 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P12IMSK Programmable Interrupt 12 P18IMSKP Mask Programmable Interrupt 18 Mask P13IMSK Pointer Programmable Interrupt 13 P17IMSKP Mask Programmable Interrupt 17 Mask Pointer P17IMSK P13MASKP Programmable Interrupt...
Page 654 Core Registers Table A-10. LIRPTL Register Bit Descriptions Name Definition Programmable Interrupt 6. Programmable Interrupt 7 Programmable Interrupt 8 Programmable Interrupt 9 P10I Programmable Interrupt 10 P11I Programmable Interrupt 11 P12I Programmable Interrupt 12 P13I Programmable Interrupt 13 P17I Programmable Interrupt 17 P18I Programmable Interrupt 18 P6IMSK...
Page 655: Program Counter Register (Pc
Registers Reference Table A-10. LIRPTL Register Bit Descriptions (Cont’d) Name Definition P7IMSKP Programmable Interrupt Mask Pointer 7. See P6IMSKP. P8IMSKP Programmable Interrupt Mask Pointer 8. See P6IMSKP. P9IMSKP Programmable Interrupt Mask Pointer 9. See P6IMSKP. P10IMSKP Programmable Interrupt Mask Pointer 10. See P6IMSKP. P11IMSKP Programmable Interrupt Mask Pointer 11.
Page 656: Program Counter Stack Register (Pcstk
Core Registers PM and DM Address Buses and DAGs Can Handle 32-Bit Addresses Program Sequencer Handles 24-Bit Addresses 21 20 18 17 17-16 = 00; IOP peripheral S Field 17-16 = 11; IOP core Bits 20-18, System (Internal) Memory System Values in this field have the following meaning: 000- Address of an IOP register 001- Address in Long Word space...
Page 657: Status Stack Register (Sts
Registers Reference Status Stack Register (STS) register is a status stack register that stores three status registers ). The register is 3x32-bit wide and 15 loca- MODE1 ASTATx ASTATy tions deep. For the and timer interrupts, the sequencer IRQ2-0 automatically pushes and pops the status stack. Note the register can only be accessed by instructions.
Page 658: Current Loop Counter Register (Curlcntr
Core Registers Table A-11. LADDR Register Bit Descriptions Bits Value 23–0 Loop Termination Address 28–24 Termination Code Reserved (always reads zero) 31–30 Loop Type Code 00 = arithmetic condition-based (not LCE) 01 = counter-based, length 1 10 = counter-based, length 2 11 = counter-based, length >...
Page 659: Timer Count Register (Tcount
Registers Reference Timer Count Register (TCOUNT) register is a non memory-mapped, universal register ( TCOUNT Ureg only). The Timer Count register contains the timer period, indicating the number of cycles between timer interrupts. For more information on how to use the register, see “Timer and Sequencing”...
Page 660: Alternate Dag Registers (Ix', Mx', Lx', Bx
Core Registers or step size by which an Index register is pre- or post-modified during a register move. Length and Base Registers (Lx, Bx) registers are non-memory-mapped, universal registers ( Ureg only). The DAGs control circular buffering operations with Length and Base registers ( –...
Page 661: Flag Value Register (Flags)
Registers Reference Table A-13. REVPID Register Bit Descriptions Bits Name Definition 3–0 Processor Identification (Read-only) PID 7–4 Silicon Silicon Revision Revision Flag Value Register (FLAGS) register is a non-memory-mapped, universal, system register FLAGS ). At reset: Ureg Sreg • bit is pin value FLG0 FLAG0...
Page 662 Core Registers pins when the bit in the register (= 1). While this bit is PPFLGS SYSCTL set, the parallel port is not operational and the four dedicated FLAG[0:3] pins switch to their alternate state— , and IRQ0 IRQ1 IRQ2 TMREXP ...
Page 663 Registers Reference Table A-14. FLAGS Register Bit Descriptions Bits Name Definition FLG0 FLAG0 Value. Indicates the state of the FLG0 pin—high if set, (= 1) or low if cleared, (= 0). FLG0O FLAG0 Output Select. Selects the I/O direction for the FLG0 pin, the flag is programmed as an output if set, (= 1) or input if cleared, (= 0).
Page 664 Core Registers Table A-14. FLAGS Register Bit Descriptions (Cont’d) Bits Name Definition FLG8 FLAG8 Value. Indicates the state of the FLAG8 pin—high if set, (= 1) or low if cleared, (= 0). FLG8O FLAG8 Output Select. Selects the I/O direction for FLAG8—output if set, (= 1) or an input if cleared, (= 0).
Page 665: System Control Register (Sysctl
Registers Reference 15 14 13 12 11 10 FLAGS (Bits 15-0) FLG7O FLG0 FLAG7 Output Select FLAG0 Value FLG7 FLG0O FLAG7 Value FLAG0 Output Select FLG6O FLG1 FLAG6 Output Select FLAG1 Value FLG6 FLG1O FLAG6 Value FLAG1 Output Select FLG5O FLG2 FLAG5 Output Select FLAG2 Value...
Page 666 Core Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SYSCTL (0x30024) IRQ0EN Reserved Flag0 Mode PPFLGS 1=FLAG0 is in IRQ0 mode Parallel Port Mode Enable 0=FLAG0 is in FLAG0 mode 1=Enable (permits core writes) 0=Disable Parallel Port.
Page 667 Registers Reference Table A-15. SYSCTL Register Bit Descriptions Bits Name Definition SRST Software Reset. Resets (when set, = 1) the processor. When a program sets (= 1) SRST, the processor responds to the non-mas- kable RSTI interrupt and clears (= 0) SRST. Reserved IIVT Internal Interrupt Vector Table.
Page 668: Emulation Registers
Core Registers Table A-15. SYSCTL Register Bit Descriptions (Cont’d) Bits Name Definition PPFLGS Parallel Port Select. 0 = Parallel port is selected. 1 = Parallel port is not selected. ADDR and DATA pins are in FLAG mode. Permits core writes. Configuring the parallel port pins to function as FLAG0-15 also causes the FLAG[0:3] pins to change to their alternate role, and TIMEXP.
Page 669 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BRKCTL (Bits 31-16) NEGIA4 Reserved Negate Instruction Address IODISABLE Breakpoint #4 Disable I/O Breakpoints 1=Enable Breakpoint 00=Breakpoint Disabled 0=Disable Breakpoint 01=WRITE Access 10=READ Access NEGIO1 11=Any Access...
Page 670 Core Registers 15 14 13 12 11 10 BRKCTL (0x30025) (Bits 15-0) NEGIA3 PA1MODE Negate Instruction Address PA1 Triggering Mode Breakpoint #3 00=Breakpoint Disabled 1=Enable Breakpoint 01=WRITE Access 0=Disable Breakpoint 10=READ Access NEGIA2 11=Any Access Negate Instruction Address DA1MODE Breakpoint #2 DA1 Triggering Mode 1=Enable Breakpoint 00=Breakpoint Disabled...
Page 671 Registers Reference Table A-16. BRKCTL Register Bit Descriptions (Cont’d) Bit # Name Function 5–4 DA2MODE DA2 Triggering Mode 00 = Breakpoint Disabled 01 = WRITE Access 10 = READ Access 11 = Any Access 7–6 IO1MODE IO1 Triggering Mode trigger on the following conditions: Mode Triggering condition 00 = Breakpoint is disabled 01 = WRITE accesses only...
Page 672: Emulation Control (Emuctl) Register
Core Registers Table A-16. BRKCTL Register Bit Descriptions (Cont’d) Bit # Name Function ENBPA Enable Program Memory Data Address Breakpoints The ENB* bits enable each breakpoint group. Note that when the ANDBKP bit is set, breakpoint types not involved in the generation of the effective breakpoint must be disabled.
Page 673 Registers Reference Table A-17. Emulation Control Register (EMUCTL) Definitions Bit # Name Function EMUENA Emulator Function Enable. Enables processor emulation func- tions. (0 = ignore breakpoints and emulator interrupts, 1=respond to breakpoints and emulator interrupts) EIRQENA Emulator Interrupt Enable. Enables the emulation logic to recog- nize external emulator interrupts.
Page 674 Core Registers Table A-17. Emulation Control Register (EMUCTL) Definitions (Cont’d) Bit # Name Function NEGDA1 Negate data memory address breakpoint #1 see NEGPA1 bit description. NEGDA2 Negate data memory address breakpoint #2 see NEGPA1 bit description. NEGIA1 Negate instruction address breakpoint #1 see NEGPA1 bit description.
Page 675 Registers Reference Table A-17. Emulation Control Register (EMUCTL) Definitions (Cont’d) Bit # Name Function 22-23 PA1MODE PA1 breakpoint triggering mode trigger on the following condi- tions: 00 = Breakpoint is disabled 01 = WRITE accesses only 10 = READ accesses only 11 = any access 24-25 DA1MODE...
Page 676: Breakpoint (Psx, Dmx, Iox) Registers
Core Registers Breakpoint (PSx, DMx, IOx) Registers (Breakpoint) registers are located in the I/O processor register set. The emulation breakpoint registers are user-accessible if the bit is set in the register. Otherwise they can be written only UMODE BRKCTL when the DSP is in emulation space or test mode. The Breakpoint regis- ters vary in size according to the address type: instruction (24-bit address), data (32-bit address), or I/O data (19-bit address).
Page 677 Registers Reference The address ranges of the emulation Breakpoint registers are negated by setting the appropriate negation bits in the register. For more EMUCTL information, see the bit description. Each breakpoint can be dis- NEGPA1 abled by setting the start address larger than the end address. Four of the breakpoints monitor the instruction address.
Page 678 Core Registers Table A-18. PSx, DMx, IOx, and EPx (Breakpoint) Registers (Cont’d) Register Function Group PMDAS Program Data Address Start PMDAE Program Data Address End IOAS I/O Address Start IOAE I/O Address End 1 Group IA = 24-bit addresses, Groups DA and PA = 32-bit addresses, Group I/O = 19-bit addresses.
Page 679 Registers Reference Table A-19. EEMUSTAT (Breakpoint Status) Register Definitions Bits Name Function STATIA3 Instruction Address Breakpoint Hit 1 = Instruction address #3 breakpoint occurs 0 = no Instruction address #3 breakpoint occurs STATIO I/O Address Breakpoint Hit 1 = I/O address breakpoint occurs 0 = no I/O address breakpoint occurs Reserved1 EEMU-...
Page 680: Eemuin Register
Core Registers 2 This bit is set and reset by the core. 3 The FIFO controller sets and resets this bit. 4 Internal hardware sets and resets this bit. EEMUIN Register register is a one-deep, 32-bit memory-mapped I/O buffer that EEMUIN is readable by the core.
Page 681 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STATIO1 DMA EP Address Breakpoint Status 15 14 13 12 11 10 EEMUINENS STATPA EEMUIN Interrupt Enable Program Memory Break- EEMUENS point Status Enhanced Emulation Feature Enable STATDA0 Status...
Page 682 Core Registers Table A-20. EEMUSTAT Register Bit Descriptions (Cont’d) Name Description STATIA0 Instruction Address Breakpoint Hit. 0 = No instruction address #0 breakpoint occurs 1 = Instruction address #0 breakpoint occurs STATIA1 Instruction Address Breakpoint Hit. 0 = No instruction address #1 breakpoint occurs 1 = Instruction address #1 breakpoint occurs STATIA2 Instruction Address Breakpoint Hit.
Page 683: Eemuout Register
Registers Reference Table A-20. EEMUSTAT Register Bit Descriptions (Cont’d) Name Description EEMUENS Enhanced Emulation Feature Enable. 0 = Enhanced emulation feature enable 1 = Enhanced emulation feature disable Reserved EEMUINENS EEMUIN Interrupt Enable. 0 = EEMUIN interrupt disable 1 = EEMUIN interrupt enable STATIO1 DMA EP Address Breakpoint Status.
Page 684: I/O Processor Registers
I/O Processor Registers while the user has control of the DSP and stops counting when the emula- tor gains control. These registers let you gauge the amount of time spent executing a particular section of code. The register extends the EMUCLK2 time can count by incrementing each time the...
Page 685 Registers Reference The bus with highest priority gets access to the IOP register, and the other buses are held off from accessing that I/O processor register group until that access been completed. Table A-21. I/O Processor Registers Register Group IOP Registers Core I/O Registers SYSCTL, REVPID, EEMUIN, EEMUSTAT, EEMUOUT, OSPID, BRKCTL, PSA1S, PSA1E, PSA2S, PSA2E, PSA3S, PSA3E, PSA4S, PSA4E,...
Page 686 I/O Processor Registers Table A-21. I/O Processor Registers (Cont’d) Register Group IOP Registers Serial Port (SP) IISP0A, IISP0B, IMSP0A, IMSP0B, CSP0A, CSP0B, CPSP0A, CPSP0B, Registers IISP1A, IISP1B, IMSP1A, IMSP1B, CSP1A, CSP1B, CPSP1A, CPSP1B, IISP2A, IISP2B, IMSP2A, IMSP2B, CSP2A, CSP2B, CPSP2A, CPSP2B, IISP3A, IISP3B, IMSP3A, IMSP3B, CSP3A, CSP3B, CPSP3A, CPSP3B, IISP4A, IISP4B, IMSP4A, IMSP4B, CSP4A, CSP4B, CPSP4A, CPSP4B, IISP5A, IISP5B, IMSP5A, IMSP5B, CSP5A, CSP5B, CPSP5A, CPSP5B...
Page 687: Power Management Registers
Registers Reference Table A-21. I/O Processor Registers (Cont’d) Register Group IOP Registers DAI Registers SRU_CLK0, SRU_CLK1, SRU_CLK2, SRU_CLK3 SRU_DAT0, SRU_DAT1, SRU_DAT2, SRU_DAT3, SRU_DAT4 SRU_FS0, SRU_FS1, SRU_FS2 SRU_PIN0, SRU_PIN1, SRU_PIN2, SRU_PIN3 SRU_EXT_MISCA, SRU_EXT_MISCB SRU_PBEN0, SRU_PBEN1, SRU_PBEN2, SRU_PBEN3 PCG_CTLA_0, PCG_CTLA_1, PCG_CTLB_0, PCG_CTLB_1, PCG_PW IDP_CTL, DAI_STAT, IDP_FIFO, IDP_DMA_I0, IDP_DMA_I1, IDP_DMA_I2, IDP_DMA_I3, IDP_DMA_I4, IDP_DMA_I5, IDP_D-...
Page 688: Power Management Control Register (Pmctl
I/O Processor Registers Power Management Control Register (PMCTL) The Power Management Control register is a 32-bit memory-mapped reg- ister. The register’s addresses is 0x2000. This register contains bits PMCTL to control phase lock loop (PLL) multiplier and Divider (both input and output) values, PLL bypass mode, and clock enabling control for peripher- als (see Table...
Page 689 Registers Reference Table A-22. PMCTL Register Bit Descriptions Bits Name Definition 5–0 PLLM PLL Multiplier. Read/Write PLLM = 0 PLL Multiplier = 64 0<PLLM<63 PLL Multiplier = PLLM CLK_CFG[1:0] Reset Value 00 = 0000110 01 = 100000 10 = 010000 11 = 000110 PLLDx PLL Divider.
Page 690 I/O Processor Registers Table A-22. PMCTL Register Bit Descriptions (Cont’d) Bits Name Definition 17:16 CRAT PLL clock ratio (CLKIN to CK). Read only. For more detail look for refer to the ADSP-2126x clock configura- tion pin description. Reset Value = CLK_CFG[1:0] 25–18 Reserved PPPDN...
Page 691: Serial Port Registers
Registers Reference Serial Port Registers The following section describes Serial Port (SPORT) registers. SPORT Serial Control Registers (SPCTLx) The SPORT Serial Control registers’ addresses are: SPCTL0 – 0xc00 SPCTL1 – 0xc01 SPCTL2 – 0x400 SPCTL3 – 0x401 SPCTL4 – 0x800 SPCTL5 –...
Page 692 I/O Processor Registers SPCTL0 (0xc00) SPCTL1 (0xc01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x800) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 (Bits 31–16) DXS_A Data Buffer Channel A Status Active Low Frame Sync 11=Full 10=Partially Full 00=Empty 1=Active Low DERR_A...
Page 693 Registers Reference SPCTL0 (0xc00) SPCTL1 (0xc01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) 15 14 13 12 11 10 (Bits 15–0) DIFS SPEN_A Data Independent TX FS SPORT Enable A (if SPTRAN=1 or RX FS (if 1=Enable SPTRAN=0) 0=Disable 1=Data Independent 0=Data Dependent DTYPE...
Page 694 I/O Processor Registers SPCTL0 (0xc00) SPCTL1 (0xc01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 SPCTL5 (0x801) DXS_A FRFS Data Buffer Channel A Status Frame on Rising Frame Sync 11=Full 10=Partially Full 1=Left Channel First (default) 00=Empty...
Page 695 Registers Reference SPCTL0 (0xc00) SPCTL1 (0xc01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) 15 14 13 12 11 10 DIFS SPEN_A Data Independent Frame Sync SPORT Enable A 1=Data Independent 1=Enable 0=Data Dependent 0=Disable Reserved Reserved OP MODE SLEN SPORT Operation Mode Serial Word Length=1 S or Left-justified Sample Pair Mode...
Page 696 I/O Processor Registers SPCTL1 (0xc01) SPCTL3 (0x401) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 SPCTL5 (0x801) RXS_A LMFS Data Buffer Channel A Status Active Low MC 11=Full 10=Partially Full 00=Empty Transmit Data valid 1=Active low FS ROVF_A 0=Active High FS...
Page 697 Registers Reference SPCTL0 (0xc00) SPCTL2 (0x400) SPCTL4 (0x800) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 TXS_A LTDV Data Buffer Channel A Status Active Low MC Transmit 11=Full 10=Partially Full 00=Empty Data valid TUVF_A 1=Active low FS 0=Active High FS...
Page 698 I/O Processor Registers When changing SPORT operating modes, programs should clear a serial port’s control register before writing new settings to the control register. Table A-23. SPCTLx Register Bit Descriptions Bits Name Definition SPEN_A Enable Channel A Serial Port. Enables if set, (= 1) or disables if cleared, (= 0) the corresponding serial port A channel.
Page 699 Registers Reference Table A-23. SPCTLx Register Bit Descriptions (Cont’d) Bits Name Definition CKRE Clock Rising Edge Select. Selects whether the serial port uses the ris- ing edge if set, (= 1) or falling edge if cleared, (= 0) of the clock sig- nal to sample data and the frame sync.
Page 700 I/O Processor Registers Table A-23. SPCTLx Register Bit Descriptions (Cont’d) Bits Name Definition FS_BOTH FS Both Enable. This bit issues WS if data is present in both trans- mit buffers, if set (= 1). If cleared (= 0), WS is issued if data is pres- ent in either transmit buffer.
Page 701: Sport Multichannel Control Registers (Spmctlxy
Registers Reference SPORT Multichannel Control Registers (SPMCTLxy) The SPORT Multichannel Control registers’ addresses are: SPMCTL01 0xc04 SPMCTL23 0x404 SPMCTL45 0x804 register is the Multichannel Control register for SPORTs 0 SPMCTL01 and 1. The register is the Multichannel Control register for SPMCTL23 SPORTs 2 and 3.
Page 702 I/O Processor Registers SPMCTL01 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 (0xc04) DMACHS1B CHNL SPORT1 Channel B Status DMA Chaining Status Current Channel Status (read-only) DMACHS1A MCEB SPORT1 Channel A Status Multichannel Enable, DMA Chaining Status B Channels DMACHS0B...
Page 703 Registers Reference SPMCTL23 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 (0x404) DMACHS3B CHNL SPORT3 Channel B Status DMA Chaining Status Current Channel Status (read-only) DMACHS3A MCEB SPORT3 Channel A Status Multichannel Enable DMA Chaining Status B Channels DMACHS2B...
Page 704 I/O Processor Registers SPMCTL45 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 (0x804) DMACHS5B CHNL SPORT3 Channel B Status DMA Chaining Status Current Channel Status (read-only) DMACHS5A MCEB SPORT3 Channel A Status Multichannel Enable DMA Chaining Status B Channels DMACHS4B...
Page 705 Registers Reference For a detailed description of the bits in the register, refer to SPMCTLxy Table A-24. Table A-24. SPMCTLxy Register Bit Descriptions Bits Name Definition MCEA Multichannel Mode Enable. Standard and Multichannel modes only. One of two configuration bits that enable and disable mul- tichannel mode on serial port channels.
Page 706 I/O Processor Registers Table A-24. SPMCTLxy Register Bit Descriptions (Cont’d) Bits Name Definition SPORT Loopback Mode. Enables if set (= 1) or disables if cleared (= 0) the channel loopback mode. Loopback mode enables developers to run internal tests and to debug applica- tions.
Page 707: Sport Transmit Buffer Registers (Txspx
Registers Reference SPORT Transmit Buffer Registers (TXSPx) The addresses of the registers are: TXSPx TXSP0A – 0xc60 TXSP0B – 0xc62 TXSP1A – 0xc64 TXSP1B – 0xc66 TXSP2A – 0x460 TXSP2B – 0x462 TXSP3A – 0x464 TXSP3B – 0x466 TXSP4A – 0x860 TXSP4B –...
Page 708: Sport Divisor Registers (Divx
I/O Processor Registers SPORT Divisor Registers (DIVx) The addresses of the registers are: DIVx DIV0 – 0xc02 DIV1 – 0xc03 DIV2 – 0x402 DIV3 – 0x403 DIV4 – 0x802 DIV5 – 0x803 The reset value for these registers is undefined. These registers contain two fields: •...
Page 709: Sport Count Registers (Spcntx
Registers Reference SPORT Count Registers (SPCNTx) The addresses of the registers are: SPCNTx SPCNT0 – 0xC15 SPCNT1 – 0xC16 SPCNT2 – 0x415 SPCNT3 – 0x416 SPCNT4 – 0x815 SPCNT5 – 0x816 The reset value for these registers is undefined. The registers pro- SPCNTx vides status information for the internal clock and frame sync.
Page 710: Sport Transmit Compand Registers (Mtxccsy
I/O Processor Registers SPORT Transmit Compand Registers (MTxCCSy) The addresses of the registers are: MTxCCSy MT0CCS0 – 0xC0D MT0CCS1 – 0xC0E MT0CCS2 – 0xC0F MT0CCS3 – 0xc10 MT2CCS0 – 0x40D MT2CCS1 – 0x40E MT2CCS2 – 0x40F MT2CCS3 – 0x410 MT4CCS0 – 0x80D MT4CCS1 –...
Page 711: Sport Receive Compand Registers (Mrxccsy
Registers Reference Each bit, 31–0, set (= 1) in one of the four registers corresponds to MRCSx an active receive channel, 127–0, on a Multichannel mode serial port. When the register activates a channel, the SPORT receives the MRxCSx word in that channel’s position of the data stream and loads the word into buffer.
Page 712: Sport Dma Index Registers (Iispx
I/O Processor Registers SPORT DMA Index Registers (IISPx) The addresses of the registers are: IISPx IISP0A – 0xC40 IISP0B – 0xC44 IISP1A – 0xC48 IISP1B – 0xC4C IISP2A – 0x440 IISP2B – 0x444 IISP3A – 0x448 IISP3B – 0x44C IISP4A – 0x840 IISP4B –...
Page 713: Sport Dma Count Registers (Cspx)
Registers Reference SPORT DMA Count Registers (CSPx) registers’ addresses are: CSPx CSP0A – 0xC42 CSP0B – 0xC46 CSP1A – 0xC4A CSP1B – 0xC4E CSP2A – 0x442 CSP2B – 0x446 CSP3A – 0x44A CSP3B – 0x44E CSP4A – 0x842 CSP4B – 0x846 CSP5A –...
Page 714: Spi Registers
I/O Processor Registers SPI Registers The following sections describe the registers associated with the Serial Peripheral Interface (SPI). SPI Port Status Register (SPISTAT) The SPI Status register ( ) is used to detect when an SPI transfer is SPISTAT complete or if transmission/reception errors occur. The register SPISTAT can be read at any time.
Page 715 Registers Reference 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 SPISTAT (0x1002) Reserved 15 14 13 12 11 10 SPIF Reserved SPI Transmit Transfer TXCOL Complete Transmit Collision Error 1=Transfer Complete 0=Transfer Active Data Buffer Status (read-only) 1=Full Multimaster Error...
Page 716 I/O Processor Registers Table A-25. SPISTAT Register Bits (Cont’d) Name Function Type Default Transmit Data Buffer Status. Indicates the TXSPI data buffer status. 0 = Empty 1 = Full ROVF Reception Error (Overflow). Set when data is received and the receive buffer is full. 1 = New data received with full RXSPI regis- ter.
Page 717: Spi Port Flags Register (Spiflg)
Registers Reference SPI Port Flags Register (SPIFLG) This register’s address is 0x1001. The reset value for this register is 0x0F80.The register is used to enable individual SPI slave select SPIFLG lines when the SPI is enabled as a master. 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 SPIFLG (0x1001) Reserved...
Page 718: Spi Control Register (Spictl)
I/O Processor Registers SPI Control Register (SPICTL) This register’s address is 0x1000. The reset value for this register is 0x0400. The SPI Control register ( ) is used to configure and enable SPICTL the SPI system. This register is used to set up SPI configurations such as selecting the device as a master or slave or determining the data transfer rate and word size.
Page 719 Registers Reference 15 14 13 12 11 10 SPICTL (0x1000) (Bits 15–0) PACKEN TIMOD 8-Bit Packing Enable Transfer Initiation Mode 1=8 to 16-bit Packing 00=Initiate Transfer by 0=No Packing Read of Receive Buffer SPIEN 01=Initiate Transfer by Write of Transmit Buffer SPI System Enable 10=Enable DMA Transfer 1=Enable...
Page 720 I/O Processor Registers Table A-27. SPICTL Register Bit Descriptions Bits Name Definition 1–0 TIMOD Transfer Initiation Mode. Defines the transfer initiation mode and interrupt generation. 00 = Initiate transfer by read of receive buffer. Interrupt active when receive buffer is full. 01 = Initiate transfer by write to transmit buffer.
Page 721 Registers Reference Table A-27. SPICTL Register Bit Descriptions (Cont’d) Bits Name Definition CLKPL Clock Polarity. 0 = Active-high SPICLK (SPICLK low is the idle state) 1 = Active-low SPICLK (SPICLK high is the idle state) SPIMS Master Select. Configures SPI module as master or slave 0 = Device is a slave device 1 = Device is a master device Open Drain Output Enable.
Page 722: Shift Registers
I/O Processor Registers Shift Registers The processor core contains two separate 32-bit shift registers—one for reception ( ) and one for transmission ( RXSR TXSR Receive Shift Register (RXSR) register is clocked on the sampling edge of the clock. The RXSR SPICLK active edge is the opposite edge from the sampling edge.
Page 723: Spi Receive Buffer Register (Rxspi)
Registers Reference SPI Receive Data Buffer Shadow Register (RXSPI_SHADOW) Use the register for the receive data buffer ( ) to debug RXSPI_SHADOW RXSPI software. The register resides at a different address from RXSPI_SHADOW , but its contents are identical to the .
Page 724: Spi Baud Rate Register (Spibaud)
I/O Processor Registers SPI Baud Rate Register (SPIBAUD) The SPI Baud Rate register’s address is 0x1005 and its reset value is unde- fined. This SPI register is a 16-bit read-write register that is used to set the bit transfer rate for a master device. When configured as a slave, the value written to this register is ignored.
Page 725: Spi Dma Registers
Registers Reference SPI DMA Registers There are five SPI DMA-specific registers which are described in the fol- lowing sections. SPI DMA Configuration (SPIDMAC) Register The SPI DMA Configuration Register contains the control bits for SPI DMA transfers. Table A-30 provides the bit descriptions for the SPIDMAC register.
Page 726 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPIDMAC (0x1084) Reserved SPICHS DMA Chain Loading Status 1=DMA Chain Pointer Loading in Progress 0=DMA Chain Idle 15 14 13 12 11 10 SPIDMAS SPIDEN DMA Transfer Status...
Page 727 Registers Reference Table A-30. SPIDMAC Register Bits Bit(s) Name Function Type Default SPIDEN DMA Enable. Enables if set (= 1) or dis- Control ables if cleared (= 0) DMA for the SPI port. SPIRCV DMA Direction. When set, the IOP emp- Control ties the RXSPI buffer, when cleared, the IOP fills the TXSPI buffer.
Page 728: Spi Dma Start Address Register (Iispi)
I/O Processor Registers Table A-30. SPIDMAC Register Bits (Cont’d) Bit(s) Name Function Type Default SPIMME SPI Multimaster Error. Set when MME is Status set in the SPISTAT register and DMA is enabled. 13:12 SPISx DMA FIFO Status 0. Indicates the status Status of the DMA FIFO as follows: 00 = FIFO empty...
Page 729: Spi Dma Word Count Register (Cspi)
Registers Reference SPI DMA Word Count Register (CSPI) This 16-bit register contains the number of DMA words to be transferred. When this register decrements from one to zero, the DMA is complete, and an interrupt may be triggered.  To prematurely end a DMA transfer, software should write the value one to the Count register so that it will decrement to zero.
Page 730: Parallel Port Registers
I/O Processor Registers Parallel Port Registers The Parallel Port peripheral in the ADSP-2126x processor includes several user-accessible registers. One register, ( ), contains control and status. PPCTL Two registers, ( ), are used for buffering receive and transmit RXPP TXPP operations.
Page 731: Parallel Port Control Register (Ppctl)
Registers Reference Parallel Port Control Register (PPCTL) The Parallel Port Control Register ( ) is used to configure and enable PPCTL the parallel port system. This register’s address is 0x1800. Figure A-33 Table A-33 describe the bits in this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PPCTL (0x1800) Reserved...
Page 732 I/O Processor Registers Table A-33. Parallel Port Register (PPCTL) Bit Definitions Name Definition Default PPEN Parallel Port Enable. Enables if set, (= 1) or disables if cleared, (= 0) the parallel port. Clearing this bit clears FIFO and status. If an , or ALE cycle has already started, it completes normally before the port is disabled.
Page 733: Parallel Port Dma Transmit Register (Txpp)
Registers Reference Table A-33. Parallel Port Register (PPCTL) Bit Definitions (Cont’d) Name Definition Default 11-10 Parallel Port FIFO Status. These read-only bits indicate the status of the parallel port FIFO as follows: 00 = RXPP/TXPP is empty 01 = RXPP/TXPP is partially full 11 = RXPP/TXPP is full PPBHD Parallel Port Buffer Hang Disable.
Page 734: Parallel Port Dma Receive Register (Rxpp)
I/O Processor Registers Parallel Port DMA Receive Register (RXPP) This register’s address is 0x1809. This is a 32-bit read-only register acces- sible by the core or the DMA controller. At the end of a data transfer, is loaded with the data in the shift register. During a DMA receive RXPP operation, the data in the register is automatically loaded into the...
Page 735: Parallel Port Dma External Modifier Address Register (Empp)
Registers Reference Parallel Port DMA External Modifier Address Register (EMPP) This register’s address is 0x1811. This 2-bit register contains the external memory DMA address modifier. It supports only +1, 0, -1. Parallel Port DMA External Word Count Register (ECPP) This register’s address is 0x1812. This 24-bit register contains the number of words in external memory to be transferred via DMA.
Page 736 I/O Processor Registers Each of these modules is separated from each other by the SRU, and their input and output signals (the “junctions”) may only be connected via the SRU. Clock Routing Control Registers (SRU_CLKx, Group A) The Clock Routing Control registers route a serial data clock, a sample clock, and signals to the SPORTs and the Input Data Port (IDP) chan- nels.
Page 737 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_CLK0 (0x2430) SPORT3_CLK_I Reserved Serial Port 3 Clock Input SPORT5_CLK_I SPORT4_CLK_I Serial Port 5 Clock Input Serial Port 4 Clock Input 15 14 13 12 11 10 SPORT0_CLK_I SPORT2_CLK_I Serial Port 0 Clock Input...
Page 738 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_CLK2 (0x2433) Reserved IDP6_CLK_I Input Data Port 6 PCG_FSA_SYNC_EN Clock Input Enable synchronization of frame sync A with external LRCLK (MISCA4_I) IDP7_CLK_I Input Data Port 7 Clock Input 15 14 13 12 11 10...
Page 739 Registers Reference Table A-34. Group A Sources – Serial Clock Selection Code Source Signal Description 00000 (0x0) DAI_PB01_O Select DAI Pin Buffer 1 as the source 00001 (0x1) DAI_PB02_O Select DAI Pin Buffer 2 as the source 00010 (0x2) DAI_PB03_O Select DAI Pin Buffer 3 as the source 00011 (0x3) DAI_PB04_O...
Page 740 I/O Processor Registers Table A-34. Group A Sources – Serial Clock (Cont’d) Selection Code Source Signal Description 11010 (0x1A) Reserved 11011 (0x1B) Reserved 11100 (0x1C) PCG_CLKA_O Select Precision Clock A Output as the source 11101 (0x1D) PCG_CLKB_O Select Precision Clock B Output as the source 11110 (0x1E) Select Logic Level Low (0) as the source 11111 (0x1F)
Page 741 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_DAT0 (0x2440) SPORT1_DA_I Reserved Serial Port 1 Data SPORT2_DA_I Channel A Input Serial Port 2 Data Channel A Input SPORT1_DB_I Serial Port 1 Data Channel B Input 15 14 13 12 11 10 SPORT0_DA_I SPORT0_DB_I...
Page 742 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_DAT2 (0x2442) Reserved 15 14 13 12 11 10 SPORT5_DA_I SPORT5_DB_I Serial Port 5 Data Serial Port 5 Data Channel B Input Channel A Input Figure A-40.
Page 743 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_DAT4 (0x2445) IDP6_DAT_I Reserved Input Data Port 6 IDP7_DAT_I Data Input Input Data Port 7 Data Input 15 14 13 12 11 10 IDP4_DAT_I IDP5_DAT_I Input Data Port 4...
Page 744 I/O Processor Registers Table A-35. Group B Sources – Serial Data (Cont’d) Selection Code Source Signal Description 001111 (0xF) DAI_PB16_O Select DAI Pin Buffer 16 as the source 010000 (0x10) DAI_PB17_O Select DAI Pin Buffer 17 as the source 010001 (0x11) DAI_PB18_O Select DAI Pin Buffer 18 as the source 010010 (0x12)
Page 745 Registers Reference Frame Sync Routing Control Registers (SRU_FSx, Group C) The Frame Sync Routing Control registers route frame sync, or a word clock, to the serial ports and IDP. Each of the frame sync inputs specified is connected to a frame sync source based on the values described in the Group C frame sync sources listed in Table A-36.
Page 746 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_FS1 (0x2452) Reserved IDP0_FS_I IDP2_FS_I Input Data Port 0 Frame Sync Input Input Data Port 2 Frame Sync Input IDP1_FS_I Input Data Port 1 Frame Sync Input 15 14 13 12 11 10 Reserved...
Page 747 Registers Reference Table A-36. Group C Sources – Frame Sync (Cont’d) Selection Code Source Signal Description 00011 (0x3) DAI_PB04_O Select DAI Pin Buffer 4 as the source 00100 (0x4) DAI_PB05_O Select DAI Pin Buffer 5 as the source 00101 (0x5) DAI_PB06_O Select DAI Pin Buffer 6 as the source 00110 (0x6)
Page 748 I/O Processor Registers Table A-36. Group C Sources – Frame Sync (Cont’d) Selection Code Source Signal Description 11100 (0x1C) PCG_FSA_O Select Precision Frame Sync A Output as the source 11101 (0x1D) PCG_FSB_O Select Precision Frame Sync B Output as the source 11110 (0x1E) Select Logic Level Low (0) as the source 11111 (0x1F)
Page 749 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PIN0 (0x2460) Reserved DAI_PB04_I DAI_PB05_I Digital Audio Interface Pin Buffer 4 Input Digital Audio Interface Pin Buffer 5 Input 15 14 13 12 11 10 DAI_PB01_I DAI_PB03_I Digital Audio Interface...
Page 750 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PIN2 (0x2462) Reserved DAI_PB14_I DAI_PB15_I Digital Audio Interface Pin Buffer 14 Input Digital Audio Interface Pin Buffer 15 Input 15 14 13 12 11 10 DAI_PB11_I DAI_PB13_I Digital Audio Interface Pin...
Page 751 Registers Reference If the bits = 18, then setting does SRU_PIN3[23:18] SRU_PIN3[30] HIGH not invert the output. If the bits = 19, then setting SRU_PIN3[29:24] does not invert the output. SRU_PIN3[31] HIGH Table A-37. Group D Sources – Pin Signal Assignments Selection Code Source Signal Description...
Page 752 I/O Processor Registers Table A-37. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description 010111 (0x17) SPORT1_DB_O Select SPORT 1B Data as the source 011000 (0x18) SPORT2_DA_O Select SPORT 2A Data as the source 011001 (0x19) SPORT2_DB_O Select SPORT 2B Data as the source 011010 (0x1A)
Page 753 Registers Reference Table A-37. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description 110000 (0x30) MISCB_2_O Select Miscellaneous Control B-2 as the source 110001 (0x31) MISCB_3_O Select Miscellaneous Control B-3 as the source 110010 (0x32) MISCB_4_O Select Miscellaneous Control B-4 as the source 110011 (0x33)
Page 754 I/O Processor Registers Miscellaneous SRU Registers (SRU_EXT_MISCx, Group E) The Miscellaneous Signal Routing registers are a very powerful and versa- tile feature of the DAI. These registers allow external pins, timers, and clocks to serve as interrupt sources or timer inputs and outputs. They also allow pins to connect to other pins, or to invert the logic of other pins.
Page 755 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXT_MISCA (0x2470) INV_MISCA5_I MISCA3_I Invert Miscellaneous External Miscellaneous Channel A 5 Channel A 3 DAI_INT_31 INV_MISCA4_I DAI Interrupt 31 Invert Miscellaneous Channel A 4 MISCA4_I* MISCA5_I** External Miscellaneous...
Page 756 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXT_MISCB (0x2471) MISCB3_I Reserved External Miscellaneous INV_MISCB5_I Channel B 3 DAI_INT_25 Invert Miscellaneous Channel B 5 DAI Interrupt 25 DAI_INT_27 FLAG10_I DAI Interrupt 27 Flag 10 Interrupt FLAG12_I...
Page 757 Registers Reference Table A-38. Group E Sources – Miscellaneous Signals Selection Code Source Signal Description 00000 (0x0) DAI_PB01_O Select DAI Pin Buffer 1 Output as the source 00001 (0x1) DAI_P02_O Select DAI Pin Buffer 2 Output as the source 00010 (0x2) DAI_P03_O Select DAI Pin Buffer 3 Output as the source 00011 (0x3)
Page 758 I/O Processor Registers Table A-38. Group E Sources – Miscellaneous Signals (Cont’d) Selection Code Source Signal Description 10011 (0x13) DAI_P20_O Select DAI Pin Buffer 20 Output as the source 10100 (0x14) TIMER0_O Select Timer 0 Output as the source 10101 (0x15) TIMER1_O Select Timer 1 Output as the source 10110 (0x16)
Page 759 Registers Reference Table A-39. Sixty-four possible signal sources can be designated for these read/write registers: • , described in Figure A-52 SRU_PBEN0 • , described in Figure A-53 SRU_PBEN1 • , described in Figure A-54 SRU_PBEN2 • , described in Figure A-55 SRU_PBEN3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
Page 760 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PBEN1 (0x2479) PBEN08 Reserved DAI Port 8 PBEN10 Pin Buffer Enable Input DAI Port 10 PBEN09 Pin Buffer Enable Input DAI Port 9 Pin Buffer Enable Input 15 14 13 12 11 10 PBEN06...
Page 761 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PBEN3 (0x247B) PBEN19 Reserved DAI Port 19 PBEN20 Pin Buffer Enable Input DAI Port 20 Pin Buffer Enable Input 15 14 13 12 11 10 PBEN16 PBEN18 DAI Port 16...
Page 762 I/O Processor Registers Table A-39. Group F Sources – Pin Output Enable (Cont’d) Selection Code Source Signal Description 001001 (0x9) SPORT0_FS_PBEN_O Select Serial Port 0 Frame Sync Output Enable as the source 001010 (0xA) SPORT0_DA_PBEN_O Select Serial Port 0 Data Channel A Output Enable as the source 001011 (0xB) SPORT0_DB_PBEN_O...
Page 763 Registers Reference Table A-39. Group F Sources – Pin Output Enable (Cont’d) Selection Code Source Signal Description 011001 (0x19) SPORT4_FS_PBEN_O Select Serial Port 4 Frame Sync Output Enable as the source 011010 (0x1A) SPORT4_DA_PBEN_O Select Serial Port 4 Data Channel A Output Enable as the source 011011 (0x1B) SPORT4_DB_PBEN_O...
Page 764: Precision Clock Generator Registers
I/O Processor Registers Precision Clock Generator Registers The Precision Clock Generator (PCG) consists of two identical units. Each of these two units (A and B) generates one clock signal ( CLKA_O ) and one frame sync ( ) output. The PCGs are con- CLKB_O FSA_O FSB_O...
Page 765 Registers Reference Table A-40. PCG_CTLA_0 Register Bit Descriptions Bits Name Description 19–0 FSADIV Divisor for Frame Sync A. 29–20 FSAPHASE_HI Phase for Frame Sync A. Represents the upper half of the 20-bit value for the channel A frame sync phase. The phase represents the number of input clocks remaining in the first frame after the signal is enabled.
Page 766 I/O Processor Registers Table A-41. PCG_CTLA_1 Register Bit Descriptions Bits Name Description 19–0 CLKADIV Divisor for Clock A. 29–20 FSAPHASE_LO Phase for Frame Sync A. Note: This field represents the lower half of the 20-bit value for the channel A frame sync phase.
Page 767 Registers Reference Table A-42. PCG_CTLB_0 Register Bit Descriptions Bits Name Description 19–0 FSBDIV Divisor for Frame Sync B. 29–20 FSBPHASE_HI Phase for Frame Sync B. This field represents the upper half of the 20-bit value for the channel B frame sync phase. The phase represents the number of input clocks remaining in the first frame after the signal is enabled.
Page 768 I/O Processor Registers Table A-43. PCG_CTLB_1 Register Bit Descriptions Bits Name Description 19–0 CLKBDIV Divisor for Clock B. 29–20 FSBPHASE_LO Phase for Frame Sync B. Note: This field represents the lower half of the 20-bit value for the channel B frame sync phase.
Page 769 Registers Reference Table A-44. PCG_PW Register (Bypass Mode) Bits Name Description STROBEA One Shot Frame Sync A. Frame sync is a pulse with duration equal to one period of MISCA2_I signal repeating at the beginning of every frame. Note: This is valid in bypass mode only. INVFSA Active Low Frame Sync Select for Frame Sync A.
Page 770: Input Data Port Registers
I/O Processor Registers Table A-45. PCG_PW Register (Normal Mode) Number of Bits Name Description 15–0 PWFSA Pulse Width for Frame Sync A. These bits are valid when not in Bypass mode. 31–16 PWFSB Pulse Width for Frame Sync B. These bits are valid when not in Bypass mode.
Page 771 Registers Reference Input Data Port Control Register (IDP_CTL) bits control the input format modes for each of the IDP_CTL[31:8] eight channels. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP_CTL (0x24B0) IDP_SMODE7 IDP_SMODE3 Serial Mode Input Select 7 Serial Mode Input Select 3...
Page 772 I/O Processor Registers Table A-46. IDP_CTL Register (Cont’d) Bits Name Description IDP_DMA_EN DMA Enable. Enables DMA on all IDP channels. IDP_CLROVR FIFO Overflow Clear Bit. Writes of 1 to this bit will clear the overflow condition in the DAI_STAT register. Because this is a write-only bit;...
Page 773 Registers Reference FIFO, the DMA channels, and the status portions of the IDP. The IDP FIFO is an eight-deep FIFO.  Channel encoding provides for eight combinations, corresponding to the eight inputs. When using Channels 1–7, this register format applies, as well as when using Channel 0 in Serial mode. When using Channel 0 in Parallel mode, refer to the descriptions of the four possible packing modes.
Page 774: Input Data Port Dma Control Registers
I/O Processor Registers  The information in this table is not valid for the case where data comes from the PDAP channel. Input Data Port DMA Control Registers Each of the eight DMA channels have an I register with an Index pointer (19 bits), an M register with an M modifier/stride (6 bits), and a C regis- ter with a count (16 bits).
Page 775: Control Register (Idp_Pdap_Ctl)
Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP_DMA_Mx (0x2410–0x2417) Reserved 15 14 13 12 11 10 MODIFIER Input Data Port DMA Channel Modifier Figure A-65. IDP_DMA_Mx Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP_DMA_Cx (0x2420–0x2427) Reserved...
Page 776 I/O Processor Registers provides a reset bit that zeros any data waiting in the packing unit to be latched into the FIFO. The bit (bit 30) causes the reset circuit to RESET strobe when asserted, and then automatically clears. Therefore, this bit always returns a value of zero when read.
Page 777 Registers Reference Table A-48. IDP_PDAP_CTL Register Bits Name Description IDP_P01_PDAPMASK Parallel Data Acquisition Port Mask 0 = Input data from DAI_01 is masked 1 = Input data from DAI_01 is un-masked IDP_P02_PDAPMASK Parallel Data Acquisition Port Mask 0 = Input data from DAI_02 is masked 1 = Input data from DAI_02 is un-masked IDP_P03_PDAPMASK Parallel Data Acquisition Port Mask...
Page 778 I/O Processor Registers Table A-48. IDP_PDAP_CTL Register (Cont’d) Bits Name Description IDP_P12_PDAPMASK Parallel Data Acquisition Port Mask 0 = Input data from DAI_12/DATA7 is masked 1 = Input data from DAI_12/DATA7 is un-masked IDP_P13_PDAPMASK Parallel Data Acquisition Port Mask 0 = Input data from DAI_13/ADDR0 is masked 1 = Input data from DAI_13/ADDR0 is un-masked IDP_P14_PDAPMASK Parallel Data Acquisition Port Mask...
Page 779: Peripheral Timer Registers
Registers Reference Table A-48. IDP_PDAP_CTL Register (Cont’d) Bits Name Description 28–27 IDP_PDAP_PACKING PACKING Selects PDAP packing mode 00 = 8 to 32 packing 01 = {11,11,10} to 32 packing 10 = 16 to 32 packing 11 = 20 to 32 packing IDP_PDAP_CLKEDGE PDAP (Rising or Falling) Clock Edge Setting this bit (= 1) causes the data to be latched on...
Page 780: Timer Configuration Registers (Tmxctl)
I/O Processor Registers Timer Configuration Registers (TMxCTL) All timer clocks are gated off when the specific timer’s configuration regis- ter is set to zero at system reset or subsequently reset by user programs. These registers are shown in Figure A-68. 15 14 13 12 11 10 TIMODE (1–0)
Page 781: Timer Status Registers (Tmxstat)
Registers Reference Timer Status Registers (TMxSTAT) The global status registers are shown in Figure A-69. Status bits TMxSTAT are sticky and require a write-one to clear operation. During a status regis- ter read access, all reserved or unused bits return a zero. Each timer generates a unique processor interrupt request signal, TIMxIRQ A common status register latches these interrupts.
Page 782 I/O Processor Registers Table A-50. TMxSTAT Register Bit Descriptions Name Description TIM0IRQ Timer 0 Interrupt Latch Write one-to-clear (also an output) TIM1IRQ Timer 1 Interrupt Latch Write one-to-clear (also an output) TIM2IRQ Timer 2 Interrupt Latch Write one-to-clear (also an output) Reserved TIM0OVF Timer 0 Overflow/Error Write one-to-clear (also an output)
Page 783: Dai Registers
Registers Reference DAI Registers The digital applications interface (DAI) is comprised of a group of periph- erals and the signal routing unit (SRU). Digital Audio Interface Status Register (DAI_STAT) register is a read-only register located at address 0x24B8. DAI_STAT The state of all eight DMA channels is reflected in the bits IDP_DMAx_STAT (bits 24–17) of the...
Page 784 I/O Processor Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_STAT (0x24B8) IDP_DMA0_STAT IDP_FIFOSZ DMA Active Status for Number of Valid Data in IDP FIFO IDP Channel 0 Reserved IDP_DMA1_STAT IDP_FIFO_OVER IDP_DMA2_STAT Overflow (Sticky) Bit IDP_DMA3_STAT...
Page 785: Dai Resistor Pull-Up Enable Register (Dai_Pin_Pullup)
Registers Reference DAI Resistor Pull-up Enable Register (DAI_PIN_PULLUP) This 20-bit read/write register is located at address 0x247D. Bits 19–0 of  this register control the enabling/disabling 22.5 K pull-up resistor on the bits. Setting a bit to one enables a pull-up resistor on the DAI_P0[19:0] corresponding pin.
Page 786 I/O Processor Registers Table A-52. DAI_PIN_PULLUP Register (Cont’d) Bits Name Description DAI_P04_PULLUP Enable/Disable 22.5 K Pull-up Resistor for DAI_P04 1 = enables pull-up on DAI_P04 0 = disables pull-up on DAI_P04 DAI_P05_PULLUP Enable/Disable 22.5 K Pull-up Resistor for DAI_P05 1 = enables pull-up on DAI_P05 0 = disables pull-up on DAI_P05 DAI_P06_PULLUP Enable/Disable 22.5 K...
Page 787 Registers Reference Table A-52. DAI_PIN_PULLUP Register (Cont’d) Bits Name Description DAI_P15_PULLUP Enable/Disable 22.5 K Pull-up Resistor for DAI_P15 1 = enables pull-up on DAI_P15 0 = disables pull-up on DAI_P15 DAI_P16_PULLUP Enable/Disable 22.5 K Pull-up Resistor for DAI_P16 1 = enables pull-up on DAI_P16 0 = disables pull-up on DAI_P16 DAI_P17 Enable/Disable 22.5 K...
Page 788 I/O Processor Registers DAI Pin Status Register (DAI_PIN_STAT) This 20-bit read-only register is located at address 0x24B9. Bits 19–0 of this register indicate the status of . Reads from bits 31–20 DAI_P[20:1] always return 0. This register is updated at ½ core clock rate. DAI_PIN_STAT (0x24B9) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_P17...
Page 789: Dai Interrupt Controller Registers
Registers Reference Table A-53. DAI_PIN_STAT Register (Cont’d) Bits Name Description DAI_P07 Provides status of DAI_P07 pin DAI_P08 Provides status of DAI_P08 pin DAI_P09 Provides status of DAI_P09 pin DAI_P10 Provides status of DAI_P10 pin DAI_P11 Provides status of DAI_P11 pin DAI_P12 Provides status of DAI_P12 pin DAI_P13...
Page 790 I/O Processor Registers The DAI Interrupt Controller is configured using three registers. Each of the 32 interrupt lines can be independently configured to trigger based on the incoming signal’s rising edge, falling edge, both or neither. Setting a bit in the registers enables the interrupt DAI_IRPTL_RE DAI_IRPTL_FE...
Page 791: Interrupt Controller
Registers Reference The following registers are used primarily to provide status of the Resident Interrupt Controller: • High Priority Interrupt Latch ( ) register, described DAI_IRPTL_H on page A-169 • Low Priority Interrupt Latch ( ) register, described DAI_IRPTL_L on page A-170 •...
Page 792 I/O Processor Registers An explicit read resets these register values to zero, except for the IDP_FI- (IDP FIFO samples exceeded interrupt) bit. The interrupt on FO_GTN_INT bit clears automatically when the condition that IDP_FIFO_GTN_INT caused the interrupt goes away. DAI_IRPTL_L (0x2489) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXTMISCA3_INT IDP_DMA6_INT...
Page 793 Registers Reference DAI_IRPTL_PRI (0x2484) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXTMISCA3_INT IDP_DMA6_INT SRU_EXTMISCA2_INT IDP_DMA7_INT SRU_EXTMISCA1_INT Reserved SRU_EXTMISCA0_INT ISRU_EXTMISCB0_INT SRU_EXTMISCB5_INT ISRU_EXTMISCB1_INT SRU_EXTMISCB4_INT ISRU_EXTMISCB2_INT SRU_EXTMISCB3_INT 15 14 13 12 11 10 IDP_DMA5_INT Reserved IDP_DMA4_INT IDP_FIFO_GTN_INT...
Page 794 I/O Processor Registers DAI_IRPTL_RE (0x2481) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXTMISCA3_INT IDP_DMA6_INT SRU_EXTMISCA2_INT IDP_DMA7_INT SRU_EXTMISCA1_INT Reserved SRU_EXTMISCA0_INT ISRU_EXTMISCB0_INT ISRU_EXTMISCB1_INT SRU_EXTMISCB5_INT ISRU_EXTMISCB2_INT SRU_EXTMISCB4_INT SRU_EXTMISCB3_INT 15 14 13 12 11 10 IDP_DMA5_INT Reserved IDP_DMA4_INT...
Page 795 Registers Reference DAI_IRPTL_FE (0x2480) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXTMISCA3_INT IDP_DMA6_INT SRU_EXTMISCA2_INT IDP_DMA7_INT SRU_EXTMISCA1_INT Reserved SRU_EXTMISCA0_INT ISRU_EXTMISCB0_INT SRU_EXTMISCB5_INT ISRU_EXTMISCB1_INT SRU_EXTMISCB4_INT ISRU_EXTMISCB2_INT SRU_EXTMISCB3_INT 15 14 13 12 11 10 IDP_DMA5_INT Reserved IDP_DMA4_INT IDP_FIFO_GTN_INT...
Page 796 I/O Processor Registers A-174 ADSP-2126x SHARC Processor Hardware Reference...
Page 797: Interrupt Vector
B INTERRUPT VECTOR ADDRESSES Table B-2 shows all the ADSP-2126x processor interrupts, listed accord- ing to their bit position in the IRPTL, LIRPTL, and IMASK registers. For more information, see “Interrupt Latch Register (IRPTL)” on page A-25, “Interrupt Register (LIRPTL)” on page A-30, and “Interrupt Mask Regis- ter (IMASK)”...
Page 798 Table B-2. ADSP-2126x Interrupt Vector Addresses Register IRPTL/ Vector Interrupt Function IMASK, Address Name LIRPTL Bit# IRPTL 0x00 EMUI Emulator (read-only, non-mas- kable); HIGHEST PRIORITY IRPTL 0x04 RSTI Reset (read-only, non-maskable) IRPTL 0x08 IICDI Illegal Input Condition Detected IRPTL 0x0C SOVFI Status loop or mode stack over- flow;...
Page 799 Table B-2. ADSP-2126x Interrupt Vector Addresses (Cont’d) Register IRPTL/ Vector Interrupt Function IMASK, Address Name LIRPTL Bit# LIRPTL 0x54 GPTMR1I General-purpose IOP Timer 1 Interrupt LIRPTL 0x58 Reserved LIRPTL 0x5C DAILI DAI Low Priority Interrupt LIRPTL 0x60 Reserved IRPTL 17, 18, 19 0x64-0x6F Reserved LIRPTL...
Page 800 ADSP-2126x SHARC Processor Core Manual...
Page 801 G GLOSSARY Autobuffering Unit (ABU). See I/O processor on page G-5 and DMA on page G-3. Arithmetic Logic Unit (ALU). This part of a processing element performs arithmetic and logic operations on fixed-point and floating-point data. Auxiliary registers. See Index Registers on page G-5.
Page 802 Buffered serial port. See Serial ports on page G-9. Bus slave or slave mode. A DSP can be a bus slave to another DSP or to a host processor. The DSP becomes a host bus slave when the HBG signal is returned.
Page 803 Delayed branches. These are JUMPS and CALL/return instructions with the delayed branches (DB) modifier. In delayed branches, no instruction cycles are lost in the pipeline, because the DSP executes the two instruc- tions after the branch while the pipeline fills with instructions from the new branch.
Page 804 DMA TCB chain loading. This is the process that the I/O processor uses for loading the TCB of the next DMA sequence into the parameter regis- ters during chained DMA. Edge-sensitive interrupt. The DSP detects this type of interrupt if the input signal is high (inactive) on one cycle and low (active) on the next cycle when sampled on the rising edge of CLKIN.
Page 805 Flag update. The DSP’s update to status flags occurs at the end of the cycle in which the status is generated and is available on the next cycle. Harvard architecture. DSPs use memory architectures that have separate buses for program and data storage. The two buses let the DSP get a data word and an instruction simultaneously.
Page 806 Interleaved data. To take advantage of the DSP’s data accesses to 4- and 3-column locations, programs must adjust the interleaving of data into (not necessarily sequential) memory locations to accommodate the mem- ory access mode. Internal memory space. This space ranges from address 0x0000 0000 through 0x0005 3FFF (Normal word).
Page 807 Memory blocks and banks. The DSP’s internal memory is divided into blocks that are each associated with different data address generators. The DSP’s external memory spaces is divided into banks, which may be addressed by either data address generator. Modified addressing. The DAG generates an address that is incremented by a value or a register.
Page 808 Neighbor Registers. In Long word addressed accesses, the DSP moves data to or from two neighboring data registers. The least-significant-32 bits moves to or from the explicit (named) register in the neighbor register pair. In forced Long word accesses (Normal word address with LW mne- monic), the DSP converts the Normal word address to Long word, placing the even Normal word location in the explicit register and the odd Nor- mal word location in the other register in the neighbor pair.
Page 809 Saturation (ALU saturation mode). In this mode, all positive fixed-point overflows return the maximum positive fixed-point number (0x7FFF FFFF), and all negative overflows return the maximum negative number (0x8000 0000). Semaphore. This is a flag that can be read and written by any of the pro- cessors sharing the resource.
Page 810 DSP's DMA controller for chained DMA operations. Tristate Versus Three-state. Analog Devices documentation uses the term “three-state” instead of “tristate” because Tristate™ is a trademarked term, which is owned by National Semiconductor.
Page 811 INDEX Numerics address bus, address fields, A-33 16-bit floating-point format, address generator, 7-26 16-bit mode, 8-9, 8-11, 8-14 addressing 16-bit to 32-bit word packing enable even short words, 5-31 (PACK), 9-54 odd short words, 5-31 32-bit data, normal word, 5-26 See post-modify, modify, bit-reverse, or 32-bit shift registers, A-100...
Page 812 Index AVS (ALU floating-point overflow) bit, (AOS) bit, 2-19 A-18 carry (AC) bit, 2-19, 3-19, A-12 AVS bit, 2-19 fixed-point overflow (AOS) bit, A-18 AZ (ALU result zero or floating-point floating-point operation (AF) bit, 2-19, underflow) bit, A-12 A-14 AZ bit, 2-19 result zero (AZ) bit, A-12...
Page 813 Index bits (continued) broadcast load mode, 5-28 nesting multiple interrupt enable broadcast mode, 10-3, 10-8 (NESTM), BRx (bit-reverse addressing) bits, 4-4, PC stack full (PCFL), A-19 BSDL (boundary scan) file, unaligned 64-bit memory access BSDL Reference Guide, 6-10 (U64MA), A-9, A-19 BTC (background telemetry channel), bit test (BTST) instruction, 2-16,...
Page 814 Index CAFRZ (cache freeze) bit, 3-8, circular buffering, length and base registers, calculating starting address (32-bit A-38 addresses), 5-17 circular buffer wrap, 4-15 CALL instructions, 3-11 circular buffer x overflow interrupt (CBxI), capacitors A-29 bypass, 15-17 CKRE bit, 9-55 decoupling capacitors, 15-17 clear, bit, 2-30...
Page 815 Index compand data in place, 9-43 CPSPI register, 7-11, A-107 companding (compressing/expanding), CPSPxx registers, A-91 1-11, 9-2, 9-42, CROSSCORE software, 1-13 compare function, 2-17 crosstalk, 15-16 complementary conditions, 3-38 CSPI register, 10-40, A-107 complementary registers, 2-47, CSPx registers, 7-24, 7-28, A-91 computational mode, 2-49...
Page 816 Index (continued) data dedicated interrupt controller in, 12-26, addressing mode, 2-49 12-27 alignment, 5-13 general-purpose (GPIO) and flags, 12-26 alignment, normal word, 5-24 GPIO pins, 12-26 alignment in busses, interrupt controller, 12-26, A-167 alignment in memory, 5-13 interrupt controller registers, A-167 buffer registers, 7-23...
Page 817 Index data format Digital Audio Interface Status extended precision normal word, 40-bit (DAI_STAT) register, A-161 floating-point, 2-14 DITFS bit, A-77 normal word, 32-bit fixed-point, 2-15 DIVEN (PLL divider enable) bit, A-66 normal word, 32-bit floating-point, 2-12 divisor See DIVx registers, serial port short word, 16-bit floating-point, 2-14 DIVx registers, 9-6, 9-45, 9-47, 9-48, 9-62,...
Page 818 Index (continued) sequences, TCB loading, 7-13 architectural overview, setting up, 7-30 serial mode, 9-67 setting up on SPORT channels, 9-68 DSxEN(3-0) bits, 10-14, 10-36, A-95 set up and initiate a chain, 7-14 DSxEN bits, 10-36 set up and initiate a chain over SPI port, DSxEN (SPI device select) bits, 10-45 7-14...
Page 819 Index EMPP register, 8-17, 15-22, A-113 endian format, 9-40, EMUCLKx register, 6-4, end-of-loop instruction address, 3-27 EMUI (emulator lower priority interrupt) enhanced emulation bit, A-28, A-29 feature enable (EEMUENS) bit, A-61 emulation (JTAG), features and bits (EEMUENS) emulator FIFO status (EEMUOUTFULLS) bit, clock See EMUCLKx register A-60 control shift (EMUCTL) register,...
Page 820 Index extended precision normal word, 5-12, FIFO 5-25 control and status, 11-14 data access, 5-48, 5-49 controlling, 11-14 data storage, FIFOFLSH bit, A-105 mixed data access, 5-25 memory data transfer, 11-15 SISD mode access, 5-51 overflow clear bit, 11-14 external device or memory SPI DMA, 10-46, 10-54 reading from,...
Page 821 Index floating-point both enable See FS_BOTH bit ALU instructions, 2-22 early vs. late, 9-37 data, 2-16, frequencies, 9-62 data format (RND32) bit, 2-12 in multichannel mode, 9-26 invalid interrupt (FLTII) bit, 3-55 internal vs. external, 9-35 invalid operation interrupt (FLTII) bit, options, 9-12, 9-34 A-29...
Page 822 Index generators, reset, 15-10 IDLE instruction, defined, global interrupt enable, GM bit, 10-42 (DAI) interrupt service routine steps, GM (get more data) bit, 10-44 11-23 GPIO and flags, 12-26 DMA control registers, A-152 GPTMR2IMSK bit, A-32 illustrated, 11-1 greater or equals (GE) condition, 3-19 reset See IDP_PDAP_RESET bit greater than (GT) condition,...
Page 823 Index IDP_PDAP_RESET bit, 11-7, A-157 IMDWx (internal memory data width) IDP_PORT_SELECT bit, 11-7, 11-19, bits, 5-12, 5-19, 5-22, 5-27 A-156 implicit operations, 5-20 IDP_PORT_SELECT bits, 11-17 broadcast load, IDP_Px_PPMASK bits, 11-17, 11-19 complementary registers, 2-47 IDP_Pxx_PPMASK bits, 11-8 long word (LW) accesses, 5-23 IDP_SMODEx bits, 11-4, 11-16, 11-19...
Page 824 Index instruction internal I/O bus arbitration (request & ADD, 2-17, 2-44 grant), 7-18 (bit), 3-63 internal memory, 5-2, 5-10, 5-29, BIT CLR, 2-30 data width (IMDWx) bits, 5-8, 5-19, bit-reverse, 5-22 instruction address breakpoint hit DMA count See CSPx registers (STATIx) bit, A-56, A-57, A-60 DMA index, 7-24,...
Page 825 Index interrupt mask interrupts (continued) control (IMASK) register, 3-55 PC stack full, 3-17 control register pointer, (IMASKP) response, 3-48 control register, 3-58 re-using, 3-60 IMASK control register, 3-64 sensitivity, interrupts, interrupt mask (IMASK) control register, software, 1-8, 3-50 A-25 timer, 3-47, 14-5 interrupt nesting enable (NESTM) bit, interrupts and sequencing,...
Page 826 Index IRPTL register, 10-33 latch IRQ2-0 pins, 15-12 characteristics, IRQxE (interrupt sensitivity) bits, status for interrupts, A-25 IRQxE (interrupt x edge/level sensitivity) latches, high and low priority, 12-29 bits, 3-53 latching interrupts, 3-55 IRQxI (hardware interrupt) bits, A-28 latchup, 15-14 ISSEN bit, 10-37, 10-40 latency, 3-9, 3-50,...
Page 827 Index long word, 5-12, 5-23, 5-25 L unit See ALU data access, 5-23, LxDEN bit, 7-30 data moves, 5-24 Lx (length) registers, 4-2, 4-16, A-38 data storage, Lx registers, single data, 5-52 SISD mode, 5-54 loop, 3-1, 3-25, making connections via the SRU, 12-15 address stack, 3-31, 3-63...
Page 828 Index memory (continued) MME bit, 10-8, 10-40, A-93 mixing 40/48-bit and 16/32/64-bit data, mnemonics See instructions 5-17 MN (multiplier negative) bit, 2-27, A-13 mixing instructions and data mode two unused locations, 5-17 timer, A-158 mixing word width in SIMD mode, 5-67 MODE1 register, mixing word width in SISD mode,...
Page 829 Index MTxCCSy registers, 9-45, 9-47, A-88 multiplier (continued) MTxCSy registers, 9-46, 9-47, A-87 input modifiers, 2-30 multichannel instructions, 2-23, 2-28 A and B channels, 9-10 MRF/B registers, 2-23, 2-24 mode, operations, 2-23, 2-27 mode of operation, 9-24 overflow (MV) bit, A-13 mode of operation, configuring, 9-27...
Page 830 Index MV (multiplier overflow) bit, 3-19 operands and results MVS bit, 2-27 storage for, A-21 MVS (multiplier floating-point overflow) operation mode See OPMODE bit bit, A-19 OPMODE bit, 9-11, 9-15, 9-20, 9-27, Mx registers, 4-2, 4-16, A-37, 9-54, A-76 or, logical, 2-17 OSPIDENS bit, A-57...
Page 831 Index parallel port, Parallel Port DMA External Index Address accessing external devices via, 8-17 (EIPP) register, 8-17 ALE polarity level See PPALEPL bit Parallel Port DMA External Modifier booting, 15-20 Address (EMPP) register, A-113 buffer hang disable See PPBHD bit Parallel Port DMA External Word Count bus status (PPBS) bit See PPBS bit (ECPP) register, 8-16,...
Page 832 Index PC stack pointer See PCSTKP register porting from previous SHARC processors, PCSTKP (program counter stack pointer) symbol changes, 1-17 register, 3-17, 3-63, 3-64 porting from previous SHARCs PCSTKP register, A-34 assembly syntax, 2-39 PCSTK (program counter stack) register, performance, 2-46 3-63, 3-64...
Page 833 Index processing element Y enable (PEYEN) bit, program sequence address (PSAx) register, SIMD mode, 2-12, 2-46, 4-4, 4-6, A-55 4-18, 5-19, 5-27 program sequencer processor control, clock frequency, latency, 3-63 core, PSAx register, A-55 core enhancements, 1-15 PSx, DMx, IOx, & EPx registers, A-55, processor core, A-58 buses,...
Page 834 Index receive data buffer shadow See registers (continued) RXSPI_SHADOW register universal, receive overflow error See SPIOVF bit universal (Ureg) registers, 2-47 receive overflow error (SPIOVF) bit, register-to-register 10-53, 10-54 moves, 2-53, Receive Shift (RXSR) register, 10-2, A-100 swaps, 2-52, reception error bit (ROVF), set in transfers, 2-50 SPISTAT register,...
Page 835 Index RXSP2B register, 9-46 selecting transmit and receive channel order RXSP3A register, 9-46 (FRFS), 9-16, 9-21 RXSP4A register, 9-48 semaphores, RXSP4B register, 9-48 SENDZ bit, 10-41 RXSP5A register, 9-48 SENDZ (send zeros) bit, 10-44 RXSPI and TXSPI buffer registers, 10-33 sensing interrupts, 3-53 RXSPI buffer,...
Page 836 Index serial port (continued) serial port transmit compand See enabling I S mode (OPMODE), 9-15, MTxCCSy registers 9-21 serial port transmit underflow status See enabling master mode (MSTR), 9-16, TUVF_A bit 9-21 serial scan path, enabling with SPCTLx registers, serial test access port (TAP), features, serial word endian select bit See LSBF bit frame sync See IFS or IRFS bit, internal...
Page 837 Index signals SPCTL4 register, 9-47 slave select (SPI), 10-49 SPCTL5 register, 9-47 signed data, 2-15 SPCTLx control bit comparison in four signed input, 2-30 SPORT operation modes, 9-51 sign extension, SPCTLx control bits for left-justify sample SIMD mode, 1-6, 1-15, 3-18, 5-28 pair mode, 9-11, 9-20...
Page 838 Index (continued) (continued) features, 10-1 transmit buffer See TXSPI register finished See SPIF bit transmit data buffer See TXSPI register functional description, 10-2 transmit underrun error (SPIUNF) bit, interconnection, 10-6 10-53, 10-54 interface signals, 10-3 TXFLSH (flush transmit buffer) bit, interrupt, 10-47 10-51...
Page 839 Index SPI device select enable See DSxEN bits SPIOVF (SPI receive overflow error) bit, SPI device select enable slave See DSxEN 10-53, 10-54 bits SPI port, 10-1 SPI DMA Address Modifier (IMSPI) clock, 10-5 register, 10-39, A-106 clock phase, 10-26 SPI DMA address modify See IMSPI DMA channel, 10-12...
Page 840 Index SPIS0 bit, A-106 SPORT (continued) SPI slave mode operation, 10-44 registers, memory-mapped IOP SPISTAT register, 10-40, A-92, A-101 addresses, 9-45 SPI status See SPISTAT register registers. listed, 9-45 SPI transfer register writes, 9-50 beginning and ending, 10-28 transmit buffer See TXSPx registers formats, 10-26 SPORT 0/1 multichannel control See...
Page 841 Index SPORT4 transmit data buffer, 9-48 SPORTs SPORT5 divisor for transmit/receive See bidirectional functions, DIV5 register registers, A-69 SPORT5 receive data buffer, 9-48 serial ports, SPORT5 serial control See SPCTL5 SPORT Serial Control (SPCTLx) registers, register 9-27, A-69 SPORT5 transmit data buffer, 9-48 SPORT Serial Port Control (SPCTLx) SPORT Chain Pointer (CPSPxx) registers,...
Page 842 Index (continued) STATDAx (data memory breakpoint hit) Group E connections, 12-23 bit, A-59 Group F connections, 12-25 STATDx bit, A-56 pin buffer, 12-7 STATI0 (I/O address breakpoint hit) bit, pin buffer as signal input pins, 12-11 A-60 pin buffer as signal output pins, 12-9 STATI0 (I/O memory breakpoint hit) bit, register groups,...
Page 843 Index SV (shifter overflow) bit, 3-19, A-14 Time-Division-Multiplexed (TDM) swap register operator, 2-52, mode, 1-11, 9-1, G-10 switching from receive to transmit DMA, serial system, 9-24 10-51 TIMEN (timer enable) bit, 3-46, switching from transmit to receive DMA, timer, 1-8, 3-46 10-50 external event watchdog (EXT_CLK)
Page 844 Index TMSTAT (timer status) register, 14-3 transmit data See TXSPI buffer TMS (test mode select) pin, transmit frame sync divisor See TFSDIV bit TMxCNT (timer count) register, 14-1 transmit shift See TXSR register TMxCTL (peripheral timer control) Transmit Shift (TXSR) register, 10-2, registers, A-158 A-100...
Page 845 Index underflow See multiplier universal registers See Ureg registers wait states universal registers (UREG), defined, G-10 unpacking (32-to-16-bit data), watchdog timer, 14-7 unpacking sequence for 32-bit data, WDTH_CAP (width capture) mode, 14-1, unsigned data, 2-15 14-10 unsigned input, 2-30 word length unsupported instructions (SLEN, WL) bits, 9-15...
Page 846 Index I-36 ADSP-2126x SHARC Processor Hardware Reference...

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