Table of Contents
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LPM Attribute Register ....................................................................................................................... 27–196
LPM Control Register ......................................................................................................................... 27–197
LPM Function Address Register .......................................................................................................... 27–199
LPM Interrupt Enable Register ........................................................................................................... 27–200
LPM Interrupt Status Register ............................................................................................................ 27–202
Low-Speed EOF 1 Register .................................................................................................................. 27–205
MPn Receive Function Address Register .............................................................................................. 27–206
MPn Receive Hub Address Register ..................................................................................................... 27–207
MPn Receive Hub Port Register .......................................................................................................... 27–208
MPn Transmit Function Address Register ........................................................................................... 27–209
MPn Transmit Hub Address Register .................................................................................................. 27–210
MPn Transmit Hub Port Register ........................................................................................................ 27–211
PHY Control Register ......................................................................................................................... 27–212
PLL and Oscillator Control Register ................................................................................................... 27–213
Power and Device Control Register ..................................................................................................... 27–214
RAM Information Register .................................................................................................................. 27–217
EPn Request Packet Count Register .................................................................................................... 27–218
Receive FIFO Address Register ............................................................................................................ 27–219
Receive FIFO Size Register .................................................................................................................. 27–220
Software Reset Register ........................................................................................................................ 27–222
Testmode Register ............................................................................................................................... 27–223
Transmit FIFO Address Register .......................................................................................................... 27–224
Transmit FIFO Size Register ................................................................................................................ 27–225
VBUS Control Register ....................................................................................................................... 27–227
VBUS Pulse Length Register ............................................................................................................... 27–228
Media Local Bus (MLB)
Features........................................................................................................................................................ 28–1
MLB Definitions ......................................................................................................................................... 28–2
Clocking ...................................................................................................................................................... 28–3
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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