Table of Contents
Advertisement
Peripheral and SCB Bridge Slave Error Response Register ..................................................................... 29–93
Bus Order Manager Watchdog Off Register .......................................................................................... 29–94
Bus Multiple Outbound Decomposition SubReq Control Register ....................................................... 29–95
ACE Cache Coherency Control Register 1 ............................................................................................. 29–96
ACE Cache Coherency Control Register 3 ............................................................................................. 29–97
PCIe Capabilities, ID, Next Pointer Register ......................................................................................... 29–98
Correctable Error Mask Register .......................................................................................................... 29–100
Correctable Error Status Register ......................................................................................................... 29–101
Device Capabilities 2 Register ............................................................................................................. 29–103
Device Control 2 and Status 2 Register ............................................................................................... 29–107
Device Control and Status Register ..................................................................................................... 29–108
DMA Read Arbitration Weight Low Off Register ................................................................................ 29–113
DMA Read Channel 1 and 0 IMWr Data Register .............................................................................. 29–114
DMA Control 1 Read Channel Register .............................................................................................. 29–115
DMA Destination Address High Read Channel Register ..................................................................... 29–118
DMA Destination Address Low Read Channel Register ...................................................................... 29–119
DMA Read Done IMWr Address High Register .................................................................................. 29–120
DMA Read Done IMWr Address Low Register ................................................................................... 29–121
DMA Read Doorbell Register .............................................................................................................. 29–122
DMA Read Engine Enable Register ..................................................................................................... 29–123
DMA Read Error Status High Register ................................................................................................ 29–125
DMA Read Error Status Low Register ................................................................................................. 29–127
DMA Read Interrupt Clear Register .................................................................................................... 29–128
DMA Read Interrupt Mask Register .................................................................................................... 29–129
DMA Read Abort IMWr Address High Register .................................................................................. 29–130
DMA Read Abort IMWr Address Low Register ................................................................................... 29–131
DMA Read Interrupt Status Register ................................................................................................... 29–132
DMA LLP High Read Channel Register .............................................................................................. 29–133
DMA LLP Low Read Channel Register ............................................................................................... 29–134
DMA Read Linked List Error Enable Register ..................................................................................... 29–135
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
lv
Advertisement
Table of Contents
