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SMPU Functional Description
Depending on the setting of the SMPU_RCTL[n].RIDCINV or the SMPU_RCTL[n].WIDCINV bits, the ID
match comparison is inverted or not. The final result after applying the inversion, SMPU_RCTL[n].RIDCINV,
or SMPU_RCTL[n].WIDCINV, determines whether the transaction bypasses the protection.
Usage
The masks,
SMPU_RIDMSKA[n]
ID and the configured ID in SMPU_RIDA[n].ID and SMPU_RIDB[n].ID, respectively. By default the masks
are zero. If ID-based region protection is enabled by setting the SMPU_RCTL[n].WPROTEN or
SMPU_RCTL[n].RPROTEN bit fields and the masks are not set, the ID comparison essentially compares zeros.
The comparison allows all transactions to bypass (if the region-based security setting is also configured in a way to
allow transactions to go through for the region). To have the ID-based region protection to function, the mask regis-
ters and ID registers must also be set.
System IDs
The System Master IDs table provides the IDs for the system masters. An x means that the bit can be a 0 or a 1.
There are multiple IDs associated with that particular system master.
Table 13-3: System Master IDs
Master Name
SPORT0_A
SPORT0_B
SPORT1_A
SPORT1_B
SPORT2_A
SPORT2_B
SPORT3_A
SPORT3_B
SPORT4_A
SPORT4_B
SPORT5_A
SPORT5_B
SPORT6_A
SPORT6_B
SPORT7_A
SPORT7_B
CRC0_CH0
13–6
and SMPU_RIDMSKB[n], are AND'ed with both the incoming transaction
SCB Input Switch
Master ID SCB Input
0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
0
8
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
ID
13'b00000000x0000
13'b00000000x0001
13'b00000000x0010
13'b00000000x0011
13'b00000000x0100
13'b00000000x0101
13'b00000000x0110
13'b00000000x0111
13'b00010000x0000
13'b00010000x0001
13'b00010000x0010
13'b00010000x0011
13'b00010000x0100
13'b00010000x0101
13'b00010000x0110
13'b00010000x0111
13'b00000000x1000
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