Analog Devices ADSP-SC58 Series Hardware Reference Manual page 714

SPI Functional Description
the number. The clock rate can be as high as the SCLK1_0 rate, and both even and odd dividers from SCLK1_0 are
supported. For master devices, the SPI uses the SPI_CLK register value to determine the clock rate, whereas this
value is ignored for slave devices.
When the SPI controller is a master, SPI_CLK is an output signal. Conversely, when the SPI controller is a slave,
SPI_CLK is an input signal. Slave devices ignore the SPI clock when the slave select input is driven inactive. The
SPI uses the SPI_CLK signal to shift out and shift in the data driven onto the SPI_MISO and SPI_MOSI lines.
The data is always shifted out on one edge of the clock (the active edge) and sampled on the opposite edge of the
clock (the sampling edge). Clock polarity and clock phase relative to data are programmable through the
register and define the transfer format.
Controlling Delay Between Frames
The SPI Timing with Lead and Lag Programming (Independent of SPI_CTL.CPHA Setting) figure illustrates SPI
timing using the SPI_DLY.LEADX and SPI_DLY.LAGX programming. The SPI uses the SPI_DLY.LAGX
bits to control the timing between the slave select (SPI_SS) signal assertion and the first SPI_CLK edge. The SPI
uses the SPI_DLY.LEADX bits to control the timing between the last SPI_CLK edge and deassertion of the
SPI_SS signal. The lead and lag timing can be extended by a 1 SPI_CLK duration to ease timing restrictions on
the slave device.
Figure 16-4: SPI Timing with Lead and Lag Programming (Independent of SPI_CTL.CPHA Setting)
16–8
1/2 SPI_CLK
SPI_SEL
1 SPI_CLK
SPI_CLK Pol - 0
SPI_CLK Pol - 1
1 1/2 SPI_CLK
SPI_SEL
1 SPI_CLK
SPI_CLK Pol - 0
SPI_CLK Pol - 1
1/2 SPI_CLK
SPI_SEL
1 SPI_CLK
SPI_CLK Pol - 0
SPI_CLK Pol - 1
1 1/2 SPI_CLK
SPI_SEL
1 SPI_CLK
SPI_CLK Pol - 0
SPI_CLK Pol - 1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SPI Timing: LEAD = 0, LAG = 0
SPI Timing: LEAD = 0, LAG = 1
1 SPI_CLK
SPI Timing: LEAD = 1, LAG = 0
1 SPI_CLK
SPI Timing: LEAD = 1, LAG = 1
SPI_CTL