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Shadow EMR1 DDR2 Register
The
register in the DMC shadows the EMR1 register in the SDRAM when the DMC is in DDR2
DMC_EMR1
mode (DMC_CTL.LPDDR =0). This register is used only when the DMC is operating in DDR2 mode.
If unmasked by the corresponding bit in the shadow mask register (DMC_MSK.EMR1 =1), a write to
triggers an extended "mode register set" command on the memory interface. If masked, a write to
updates the register in the DMC, not the register in the SDRAM.
QOFF (R/W)
Output Buffer Enable
DQS (R/W)
LDQS/UDQS Enable
RTT1 (R/W)
RTT Termination Resistance 1
AL (R/W)
Additive Latency
Figure 10-10: DMC_EMR1 Register Diagram
Table 10-19: DMC_EMR1 Register Fields
Bit No.
(Access)
12
QOFF
(R/W)
10
DQS
(R/W)
6
RTT1
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Output Buffer Enable.
The DMC_EMR1.QOFF bit enables the SDRAM output pins. For more information
about this operation, see the data sheet for the SDRAM being used in your system.
LDQS/UDQS Enable.
The DMC_EMR1.DQS bit enables the single ended operation of the DMC_LDQS/
DMC_LDQS or DMC_UDQS/DMC_UDQS pin. For more information about this opera-
tion, see the data sheet for the SDRAM being used in your system.
The DDR Controller enables differential signaling mode (EMR1) by default. Because
the controller supports differential signaling mode only, setting this bit is not allowed.
RTT Termination Resistance 1.
The DMC_EMR1.RTT1 bit combines with the DMC_EMR1.RTT0 bit to set the ter-
mination resistance. See the DMC_EMR1.RTT0 bit description for more information.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
0 Enable
1 Disable
ADSP-SC58x DMC Register Descriptions
DLLEN (R/W)
DLL Enable
DIC (R/W)
Output Driver Impedance Control
RTT0 (R/W)
Termination Resistance 0
DMC_EMR1
only
DMC_EMR1
10–39
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