Analog Devices ADSP-SC58 Series Hardware Reference Manual page 945

Architectural Concepts
-PWM_TMy/2
0 +PWM_TMy/2
+PWM_TMy/2
0
PWM_TM PWM_TM
PWM_AH
FULL ON
PWM_AL
2 × DT
EMERGENCY DEADTIME
PULSEMODE 10
Figure 19-16: Over Modulation Transition Example
Gate Drive Unit
The gate drive unit of the PWM adds features that simplify the design of isolated gate drive circuits for PWM inver-
ters. When using a transformer coupled power device gate drive amplifier, the active PWM signal must be chopped
at a high frequency. The register allows the programming of this chopping mode for high frequen-
PWM_CHOPCFG
cy. The chopped active PWM signals can be required for the high-side drivers only, for the low-side drivers only, or
for both the high-side and low-side switches. Therefore, independent control of this mode for both high and low-
side switches is included with two separate control bits in the register.
PWM_CHANCFG
The High-Side and Low-Side Outputs With Gate Chop Enabled figure shows the typical PWM output signals with
high-frequency chopping enabled on both high-side and low-side signals. Chopping of the PWM outputs is enabled
by setting bits in PWM_CHANCFG register. The 8-bit PWM_CHOPCFG.VALUE value controls the high frequency
chopping. The following equation gives the period of this high frequency carrier.
T = [4 × (CHOPDIV + 1)] × t
chop CK
and the chopping frequency is therefore an integral subdivision of the peripheral clock frequency:
f = f /[4 × (CHOPDIV + 1)]
chop CK
The PWM_CHOPCFG.VALUE value can range from 0 to 255, corresponding to a programmable chopping frequen-
cy rate from 122 kHz to 31.25 MHz for a 125 MHz, f rate. Program the gate drive features before enabling the
CK
PWM controller. Do not change the gate drive features during normal operation of the controller. Following a reset,
clear all bits of the register so that high frequency chopping is disabled, by default.
PWM_CHANCFG
-PWM_TM/2
0 +PWM_TM/2
+PWM_TM/2
0
COUNT
PWM_CH0
PWM_CH0
PWM_AH
PWM_AL
2 × DT
2 × DT
Figure 19-17: High-Side and Low-Side Outputs With Gate Chop Enabled
19–24 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference