Analog Devices ADSP-SC58 Series Hardware Reference Manual page 635

Table 14-23: PORT_POL Register Fields (Continued)
Bit No.
(Access)
7 PX7
(R/W)
6 PX6
(R/W)
5 PX5
(R/W)
4 PX4
(R/W)
3 PX3
(R/W)
2 PX2
(R/W)
1 PX1
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Port x Bit 7 Polarity Invert.
The PORT_POL.PX7 bit enables polarity inversion.
Port x Bit 6 Polarity Invert.
The PORT_POL.PX6 bit enables polarity inversion.
Port x Bit 5 Polarity Invert.
The PORT_POL.PX5 bit enables polarity inversion.
Port x Bit 4 Polarity Invert.
The PORT_POL.PX4 bit enables polarity inversion.
Port x Bit 3 Polarity Invert.
The PORT_POL.PX3 bit enables polarity inversion.
Port x Bit 2 Polarity Invert.
The PORT_POL.PX2 bit enables polarity inversion.
Port x Bit 1 Polarity Invert.
The PORT_POL.PX1 bit enables polarity inversion.
ADSP-SC58x PORT Register Descriptions
Description/Enumeration
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
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