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Efficiency Controller
transactions while scheduling. When the page-based scheduling of the buffered transactions is complete, same mas-
ter transaction scheduling is triggered. If multiple transactions from a master are received, the efficiency controller
schedules the transactions back-to-back.
DMC Read Data Buffer
The DMC read data buffer contains a data buffer and an address buffer. The depth of the data buffer is equal to the
burst length that is programmed in SDRAM. The address buffer holds the corresponding SDRAM burst address.
When an SDRAM write address from any master matches an address in the DMC read data buffer, the DMC inva-
lidates the related data in the read buffer. When the
is programmed with a value other than zero, the DMC read data buffer operation is enabled. The set of masters
whose data is buffered and retrieved are programmed in the
registers. The DMC can use the
of masters similar to the programming of the
See the
SCB ID-Based Priority
Closed Page Per Bank
The
register provides per-bank granularity for closing pages. The software can determine that most
DMC_EFFCTL
accesses to a given bank in memory always result in a missed page. In this case, set the PREC_BANK bit correspond-
ing to the required bank to close the row after every transfer. This proactive step can result in reduced thrashing and
increases memory throughput.
SCB ID-Based Priority
The primary goal of the dynamic memory controller is to improve sustainable memory system bandwidth so that
the service time for the average request can be reduced. However, to service critical requests from any master in the
system, the DMC provides a mechanism to elevate priority of a given access. The DMC priority ID registers
(DMC_PRIO
and DMC_PRIO2) can be programmed with up to two SCB IDs with elevated priority.
After every access in a snapshot, the command buffers are searched to determine whether a commands ID matches
with the ID programmed in the
the subsequent access in the snapshot if:
• A match occurs, and
• The direction of the access (for example write) is the same as the direction of the snapshot (write)
There is an alternative to providing priority to a specific SCB ID. If a number of IDs from the same master require
priority, program the DMC priority mask ID registers
sponding bits are 0. The DMC uses a combination of the
DMC_PRIOMSK/DMC_PRIOMSK2
By default, none of the IDs are prioritized. The following are a few possibilities.
• The
DMC_PRIOMSK
field to 0xFFFFFFFF and set the
• If the
DMC_PRIOMSK
10–6
DMC_RDDATABUFMSK1
DMC_PRIOMSK
section for details.
DMC_PRIO
and
DMC_PRIO2
registers to elevate the priority of a select few or all IDs that belong to a master.
field is set to 0x00000000. If a single ID (7234) needs priority, set the
DMC_PRIO
field is set to 0xFFFFFFFE, the SCB IDs 7234 and 7235 are given priority.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMC_RDDATABUFMSK1
DMC_RDDATABUFID1
and
DMC_RDDATABUFMSK2
and
DMC_PRIOMSK2
registers. The priority SCB ID access is sent before
(DMC_PRIOMSK
and DMC_PRIOMSK2) so that the corre-
DMC_PRIO
and
field to 7234.
or
DMC_RDDATABUFMSK2
or
DMC_RDDATABUFID2
ID registers to select a set
registers.
DMC_PRIO2
registers and the
DMC_PRIOMSK
register
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