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17 Universal Asynchronous Receiver/Trans-
mitter (UART)
The UART module is a full-duplex peripheral compatible with PC-style industry-standard UARTs. The UART con-
verts data between serial and parallel formats. The serial communication follows an asynchronous protocol that sup-
ports various word lengths, stop bits, bit rates, and parity-generation options. Multiple events can generate inter-
rupts.
The UART is logically compliant to EIA-232E, EIA-422, EIA-485 and LIN standards, but usually requires external
transceiver devices to meet electrical requirements. In IrDA (Infrared Data Association) mode, the UART meets the
half-duplex IrDA SIR (9.6/115.2 Kbps rate) protocol. In multi-drop bus mode, the UART meets the full-duplex
MDB/ICP v2.0 protocol.
The UART module supports partial modem status and control functionality to allow for hardware flow control.
The UART is a DMA-capable peripheral with separate transmit and receive DMA master channels. The use of
DMA requires minimal software intervention as the DMA engine moves the data. The UART can also use a pro-
grammed core mode of operation. The core mode requires software management of the data flow using either inter-
rupts or polling.
The UART can use one of the peripheral timers for a hardware-assisted auto-baud detection mechanism. The timers
are external to the UART.
UART Features
Each UART includes the following features.
• 5–8 data bits
• Programmable extra stop bit and programmable extra half-stop bit
• Even, odd, and sticky parity bit options
• Extra 8-stage receive FIFO with programmable threshold interrupt request
• Flexible transmit and receive interrupt request timing
• Three interrupt outputs for receive, transmit, and status
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Universal Asynchronous Receiver/Transmitter (UART)
17–1
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