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System Memory (L2CTL/DMC/SMC/OTPC/SMPU)
System MMR Write-Protection (WP48) from SPU
Enable Secure Peripheral (SECUREP48) from SPU
Figure 1-9: SMC System Diagram
One-Time Programmable Memory Controller (OTPC)
The
One-Time Programmable Memory Controller (OTPC)
ory core with a programming controller, charge pump, and voltage regulator. A built-in Hamming Code Error Cor-
rection (ECC), and a fully implemented double-redundant program or read scheme protect the OTP data.
Figure 1-10: OTPC System Diagram
System Memory Protection Unit (SMPU)
The
System Memory Protection Unit (SMPU)
write access from any or all masters in the system. In addition, it can guard against memory access depending on
security privileges of the system master.
On the ADSP-SC58x, 10 SMPU instances are available to protect the L2, external memory (DMC/SMC), and
memory-mapped I/O (PCIe) interfaces. Six instances are allotted to protect the L2 memory, two instances for
DMC0 and DMC1, one instance for SMC and one instance for PCIe.
System MMR Write-Protection for SMC (WP49) from SPU
Enable Secure Peripheral for SMC (SECUREP49) from SPU
System MMR Write-Protection for L2CTL (WP118-123) from SPU
Enable Secure Peripheral for L2CTL (SECUREP118-123) from SPU
System MMR Write-Protection for PCIe (WP139) from SPU
Enable Secure Peripheral for PCIe (SECUREP139) from SPU
System MMR Write-Protection for DMC (WP146-147) from SPU
Enable Secure Peripheral for DMC (SECUREP146-147) from SPU
Figure 1-11: SMPU System Diagram
1–6
System Memory Protection from SMPU0
Clocked by SCLK0_0 form CGU0
Clocked by SCLK0
System MMR Write-Protection (WP59) from SPU
Enable Secure Peripheral (SECUREP59) from SPU
Clocked by SYSCLK_0 from CGU0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMC
SMC Address Pins (SMC0_A25:01, on PORT Pins)
SMC Data Pins (SMCx_D15:00, on PORT Pins)
∙ Core/Cache Access Arbitration in SCB0 Only
∙ DMA Access Arbitration Among Numerous SCBs
SMC Control/Reference Pins
∙ All SMCx_ Signals Not Detailed Above (on PORT Pins)
module is a complete system integrating an OTP mem-
OTPC
provides a flexible way of protecting memory regions against read or
SMPU
Dual-Bit Error (OTPC0_ERR) to SEC/GIC
Aggregated Event (SMPU0_AGGR_INT) to SEC/GIC
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