Analog Devices ADSP-SC58 Series Hardware Reference Manual page 545

Table 13-4: Supported Memory Region Size and Alignment (Continued)
Size
4KB
8KB
16KB
32KB
64KB
128KB
256KB
512KB
1MB
2MB
4MB
8MB
16MB
32MB
64MB
128MB
256MB
512MB
1GB
2GB
4GB
For the case where the region size is selected as 4 GB, the region address must be at address 0x00000000.
If a memory region address is not aligned to its size, the memory region start address protected by the
NOTE:
SMPU is the configured address with the corresponding least significant bits masked. For example, if the
size is configured for 16 KB (SMPU_RCTL[n].SIZE =0b00010), and the base address is configured for
SMPU_RADDR[n].BADDR=0x00005018, the actual base address used by the SMPU is 0x00004000.
When SMPU_RADDR[n].BADDR is read back, the program reads 0x00005000. This functionality is be-
cause only bits [11:0] are reserved as 0's. Programs must use care when setting the base address as it is not
always the true base address.
SMPU Definitions
To make the best use of the SMPU, it is useful to understand the terms in this section.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMPU_RCTLn.SIZE
0b00001
0b00010
0b00011
0b00100
0b00101
0b00110
0b00111
0b01000
0b01001
0b01010
0b01011
0b01100
0b01101
0b01110
0b01111
0b10000
0b10001
0b10010
0b10011
0b10100
Address
0xXXXXN000
0xXXXXN000
0xXXXXN000
0xXXXX0000
0xXXXN0000
0xXXXN0000
0xXXXN0000
0xXXX00000
0xXXN00000
0xXXN00000
0xXXN00000
0xXX000000
0xXN000000
0xXN000000
0xXN000000
0xX0000000
0xN0000000
0xN0000000
0xN0000000
0x00000000
SMPU Functional Description
Possible Values for N
0x0, 0x2, 0x4, 0x8, 0xA, 0xC, 0xE
0x0, 0x4, 0x8, 0xC
0x0, 0x8
-
0x0, 0x2, 0x4, 0x8, 0xA, 0xC, 0xE
0x0, 0x4, 0x8, 0xC
0x0, 0x8
-
0x0, 0x2, 0x4, 0x8, 0xA, 0xC, 0xE
0x0, 0x4, 0x8, 0xC
0x0, 0x8
-
0x0, 0x2, 0x4, 0x8, 0xA, 0xC, 0xE
0x0, 0x4, 0x8, 0xC
0x0, 0x8
-
0x0, 0x2, 0x4, 0x8, 0xA, 0xC, 0xE
0x0, 0x4, 0x8, 0xC
0x0, 0x8
-
13–9