Analog Devices ADSP-SC58 Series Hardware Reference Manual page 232

Sharc+ processor
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Message Register
The
is a general-purpose register. It is intended to provide flexibility for Boot ROM code and to pass
RCU_MSG
predefined variables to the debugger. Please see the Booting chapter for product-specific details.
C2IDLE (R/W)
Core 2 Idle
C1IDLE (R/W)
Core 1 Idle
CALLERR (R/W)
Call Error Flag
CALLBACK (R/W)
Callback Call Flag
CALLINIT (R/W)
Call Initcode Flag
CALLAPP (R/W)
Call Application Flag
HALTONERR (R/W)
Halt on Error Call
HALTONCALL (R/W)
Halt on Callback Call
HALTONINIT (R/W)
Halt on Initcode Call
HALTONAPP (R/W)
Halt on Application Call
Figure 6-5: RCU_MSG Register Diagram
Table 6-10: RCU_MSG Register Fields
Bit No.
(Access)
31
CALLERR
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Call Error Flag.
The RCU_MSG.CALLERR bit indicates that a flag has been set by the boot code prior
to an error call.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Flag not set
1 Flag set
ADSP-SC58x RCU Register Descriptions
1
0
0
0
ERRCODE (R/W)
ROM Error Code
C0IDLE (R/W)
Core 0 Idle
17
16
0
0
C0L1INIT (R/W)
Core 0 L1 Initialized
C1L1INIT (R/W)
Core 1 L1 Initialized
C2L1INIT (R/W)
Core 2 L1 Initialized
C1ACTIVATE (R/W)
Core 1 Activated
C2ACTIVATE (R/W)
Core 2 Activated
SECINIT (R/W)
SEC Initialized
L2INIT (R/W)
L2 Initialized
6–15

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