Analog Devices ADSP-SC58 Series Hardware Reference Manual page 772

ADSP-SC58x SPI Register Descriptions
Table 16-31: SPI_RXCTL Register Fields (Continued)
Bit No.
(Access)
13:12 RRWM
(R/W)
8 RDO
(R/W)
6:4 RDR
(R/W)
3 RWCEN
(R/W)
16–66
Bit Name
Receive FIFO Regular Watermark.
The SPI_RXCTL.RRWM bits select the receive FIFO (SPI_RFIFO) watermark level
for regular data bus requests. When an urgent
with SPI_RXCTL.RUWM, the SPI_RXCTL.RRWM selection is used as the deasser-
tion condition for any SPI_ILAT.RUWM interrupts that are latched.
Receive Data Overrun.
The SPI_RXCTL.RDO bit selects handling for receive data requests when the receive
buffer (SPI_RFIFO) is full. If enabled and
old data in the buffer with incoming data. If disabled and
keeps old data in the buffer and discards incoming data.
Receive Data Request.
The SPI_RXCTL.RDR bits select receive FIFO (SPI_RFIFO) watermark condi-
tions that direct the SPI to generate a receive data request.
Receive Word Counter Enable.
The SPI_RXCTL.RWCEN bit enables the decrement of the
the count is not zero and SPI_RXCTL.RTI is enabled. Enabling
SPI_RXCTL.RWCEN prevents receive overrun errors from occurring. The
SPI_RXCTL.RWCEN bit is valid only when the SPI is a master.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
SPI_RFIFO
0 Empty RFIFO
1 RFIFO less than 25% full
2 RFIFO less than 50% full
3 RFIFO less than 75% full
SPI_RFIFO
0 Discard incoming data if SPI_RFIFO is full
1 Overwrite old data if SPI_RFIFO is full
0 Disabled
1 Not empty RFIFO
2 25% full RFIFO
3 50% full RFIFO
4 75% full RFIFO
5 Full RFIFO
6 Reserved
7 Reserved
0 Disable
1 Enable
watermark is enabled
is full, the SPI overwrites
is full, the SPI
SPI_RFIFO
SPI_RWC register when