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Mask (Mode Register Shadow) Register
The
register permits masking (disabling) writes to the MR and EMRn registers in the SDRAM. When
DMC_MSK
masked, writes to these registers go instead to shadow copies of these registers (DMC_MR, DMC_EMR1,
DMC_EMR2), which are maintained within the DMC. When a shadow register's corresponding bit is unmasked
(enabled), the DMC generates the MRS or EMRS command to transfer the contents of the shadow register (in the
DMC) to the actual register (in the SDRAM).
EMR3 (R/W)
Shadow EMR3 Unmask
EMR2 (R/W)
Shadow EMR2 Unmask
Figure 10-15: DMC_MSK Register Diagram
Table 10-24: DMC_MSK Register Fields
Bit No.
(Access)
11
EMR3
(R/W)
10
EMR2
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Shadow EMR3 Unmask.
The DMC_MSK.EMR3 bit masks or unmasks writes to the EMR3 register (in DDR2)
in the SDRAM. When masked, writes to this register instead go to the EMR3 register.
When unmasked, the DMC writes the EMR3 value to the EMR3 register (in DDR2)
in the SDRAM. After completing the write, the DMC clears this bit. Note that this bit
must not be enabled when in LPDDR mode (DMC_CTL.LPDDR =1).
Shadow EMR2 Unmask.
The DMC_MSK.EMR2 bit masks or unmasks writes to the EMR2 register (in DDR2)
or the EMR register (in LPDDR) in the SDRAM. When masked, writes to this regis-
ter instead go to the
DMC_EMR2
in the SDRAM. After completing the write, the DMC clears this bit.
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
0 Mask (Disable) Write to EMR3
1 Unmask (Enable) Write to EMR3
register. When unmasked, the DMC writes the
DMC_EMR2
value to the EMR2 register (in DDR2) or the EMR register (in LPDDR)
0 Mask (Disable) Write to EMR2
1 Unmask (Enable) Write to EMR2
ADSP-SC58x DMC Register Descriptions
0
0
MR (R/W)
Shadow MR Unmask
EMR1 (R/W)
Shadow EMR1 Unmask
16
0
10–51
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