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UART Event Control
When enabled by the UART_IMSK.ETBEI bit, the UART_STAT.THRE flag requests data along the peripheral
command lines to the DMA controller (referred to as TXREQ). This signal is routed through the DMA controller.
If the associated DMA channel is enabled, the TXREQ signal functions as a DMA request, otherwise the DMA
controller simply forwards it to the SEC. Alternatively the UART_IMSK.ETXS bit can redirect the transmit inter-
rupts to the UART status interrupt.
With interrupts disabled, the UART module can poll the status flags to determine when data is ready to move. Be-
cause polling is processor intensive, it is not typically used in real-time signal processing environments. Since read
operations from
UART_STAT
without mutual impacts.
Polling the
SEC_SSTAT[n]
nate method of operation to consider. Software can write up to two words into the
bling the UART clock. As soon as the UART_CTL.EN bit is set, the UART module sends those two words.
Receive Interrupts
The UART module uses the UART_IMSK_SET.ERBFI bit to enable receive interrupt requests. If set, the
UART_STAT.DR flag requests an interrupt on the dedicated RXREQ output, indicating that new data is available
in the
register. This signal is routed through the DMA controller. If the associated DMA channel is
UART_RBR
enabled, the RXREQ signal functions as a DMA request; otherwise the DMA controller simply forwards it to the
SEC. Alternatively, if no DMA channel is assigned to the UART, the UART_IMSK.ERXS bit can redirect the re-
ceive interrupts to the UART status interrupt. When software reads the
UART_STAT.DR bit again, which, in turn, clears the receive interrupt request.
Figure 17-10: Receive Interrupts
Hardware updates the following:
• UART_STAT.DR bits
• UART_STAT.ADDR bits
• UART_STAT.ASTKY bits
• UART_STAT.PE bits
17–20
registers have no side effects, different software threads can interrogate these registers
register without enabling the interrupts by the
PERIPHERAL
BUS
MEMORY
P2P
DMA FIFO
RBR
2
1
DMA_DONE=1
ERBFI:
DR set
ELSI:
PE, FE, & BI set
EAWI:
DR = ADDR = set
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC_CCTL[n]
UART_THR
UART_RBR
RX BUFFER
RX FIFO
RSR
3
4
5
ERFCI:
ERFCI:
ELSI:
RFIT=0
RFIT=1
OE set
register is an alter-
register before ena-
register, hardware clears the
RX
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