Analog Devices ADSP-SC58 Series Hardware Reference Manual page 444

ADSP-SC58x DMC Register Descriptions
Table 10-18: DMC_EFFCTL Register Fields (Continued)
Bit No.
(Access)
8 PRECBANK0
(R/W)
10–38
Bit Name
Precharge Bank 0.
The DMC_EFFCTL.PRECBANK0 bit enables precharge (closes the page) of bank 0
after each transfer if the DMC precharge feature is enabled (DMC_CTL.PREC =1).
Note: The (DMC_CTL.PREC) takes precedence over value in this register. If
(DMC_CTL.PREC =1) then all banks are precharged.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable Precharge Bank 0
1 Enable Precharge Bank 0