Cgu Operating Modes; Cgu Power-Up Sequence; Cgu Event Control - Analog Devices ADSP-SC58 Series Hardware Reference Manual

CGU Operating Modes

CGU Operating Modes
The CGU does not have configurable operating modes, but CGU operations affect the operating modes of other
modules. Some CGU operation issues that affect operation of other modules include the following:
• The PLL of the CGU operates in either normal mode (CGU clock divisors applied) or bypass mode (CGU
PLL is bypassed and clock divisors ignored).
• The SCB uses the CGU for clock synchronization across clock domains. For more information, see
Crossbars (SCB).
• The DPM uses the CGU for clock management as power state transitions occur. For more information, see the
Dynamic Power Management (DPM) chapter.
• The CGU uses clock gating control to obtain flexible low-power modes.

CGU Power-up Sequence

See the product data sheet for exact power-up requirements. The processor is configured to come up in clock bypass
mode. The programs is required to configure full speed clocks and safety monitors. CLKIN0 and all supplies should
be stable before the SYS_HWRST signal is deasserted. CLKIN1 should be stable before operation of OCU safety
unit.

CGU Event Control

The CGU generates an event or error for several different reasons.
CGU Events
After a frequency change, a CGU event indicates that the PLL has locked and clocks are synchronized. If a core was
idled while changing frequencies, the CGU can use an event interrupt to break the core idle. While in active mode,
a CGU event indicates that the PLL has locked.
CGU Errors
A CGU error occurs under following conditions:
• A write access to the
aligning the clocks.
The CGU_STAT.WDIVERR bit state indicates this error. If this error occurs, clear the
CGU_STAT.WDIVERR bit and rewrite the desired values to the
• A change to the
CGU_DIV
The CGU_STAT.WDIVERR bit state indicates this error. If this error occurs, clear the
CGU_STAT.WDIVERR bit and rewrite the desired values to the
3–6
CGU_DIV register triggers an alignment sequence while the PLL is locked and is still
register occurs while the PLL is locked and is still aligning the clocks
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CGU_DIV register.
register.
CGU_DIV
System