Analog Devices ADSP-SC58 Series Hardware Reference Manual page 721

Figure 16-12: SPI Transfer Protocol in Fast Mode for SPI_CTL.CPHA = 1
Memory-Mapped Mode (SPI2 only)
The SPI supports direct memory-mapped read accesses from a SPI memory device, enabled by setting the
SPI_CTL.MMSE bit. This mode allows for direct execution of instructions from a SPI memory device without the
need for a low-level software driver, as hardware handles all overhead tasks (for example, transmission of the read
header, pin turnaround timing, and receive data sizing). The SPI features configurable options in the memory-map-
ped read header register (SPI_MMRDH) to provide compatibility with a wide range of SPI memory devices.
In non-memory-mapped mode, the software is responsible for providing the command and required dummy words
for the read response, whereas this is all handled by hardware when the SPI is in memory-mapped mode. The mem-
ory of the SPI device is accessible directly through reads of the processor address space. The read accesses can be
code or data accesses in core mode or when using memory DMA (MDMA). These accesses allow code to execute
directly from SPI memory devices (true eXecute-In-Place operations), and the contents can be cached to improve
performance. It is not necessary to access the SPI data buffer registers nor poll status bits; however, the hardware
does not support peripheral DMA accesses nor write operations to the SPI memory space.
The Types of Operations table is a comparison of the permitted operations in the non-memory-mapped and memo-
ry-mapped modes supported by the SPI controller.
Table 16-6: Types of Operations
SPI Operation
Core data write
Core data read
Code fetch: Execute-In-Place (XIP)
Read/Write accesses using SPI Peripheral DMA
Read/Write accesses by other peripheral DMA chan-
nels
MDMA read
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CPOL=0
CPOL=1
MOSI
D6 D5
D7
MISO
D6 D5
D7
Non-Memory-Mapped Mode
Yes
Yes
No
Yes
No
No
D1
D3 D0
D4 D2
D1
D3 D0
D4 D2
Note : Last Master sample edge
is internally generated to latch
incoming data
Memory-Mapped Mode
No
Yes
Yes
No
No
Yes
SPI Functional Description
16–15