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3 Clock Generation Unit (CGU)
The Clock Generation Unit (CGU) includes the phase locked loop (PLL) and the PLL control unit (PCU). The
PLL generates a master clock that runs at a frequency that is a multiple of the CLKIN input clock frequency. The
PCU divides down the master clock to generate various system clocks and synchronization signals.
CGU Features
The CGU module supports the following features:
• Provides smooth transitions from the current clock condition to a new condition with PLL logic and executes
the changes to clocks due to register programming
• Provides PLL and clock domain status reporting for event management
• Supports the capability to bypass the PLL for power savings
• Manages power dynamically through software, allowing the dynamic control of the core clock frequency
(f
) of the processor
CCLK
• Controls clock gating of core and system clocks
NOTE:
For more information about processor-specific CGU features, see the processor data sheet.
CGU Functional Description
The CGU generates all on-chip clocks and synchronization signals based on the programmed PLL multiplication
factor and dividers. The CGU provides the following functionality.
Change the PLL clock frequency
The CGU allows programs to change the PLL clock frequency by writing new values to bits in the control
register. Any time the PLL relocks, the CGU aligns all core and system clocks.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Clock Generation Unit (CGU)
3–1
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