Analog Devices ADSP-SC58 Series Hardware Reference Manual page 100

Sharc+ processor
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ADSP-SC58x HAE Register Descriptions ................................................................................................. 49–17
Configuration 0 Register ....................................................................................................................... 49–18
Configuration 1 Register ....................................................................................................................... 49–19
Configuration 2 Register ....................................................................................................................... 49–20
Configuration 3 Register ....................................................................................................................... 49–22
Configuration 4 Register ....................................................................................................................... 49–23
DIDT Coefficient Register .................................................................................................................... 49–24
DIDT Gain Register .............................................................................................................................. 49–25
Harmonic n Index Register .................................................................................................................... 49–26
I (Current) Sample Register ................................................................................................................... 49–27
I (Current) Waveform Register .............................................................................................................. 49–28
Run Register .......................................................................................................................................... 49–29
Status Register ....................................................................................................................................... 49–30
Voltage Level Register ............................................................................................................................ 49–31
V (Voltage) Sample Register ................................................................................................................... 49–32
V (Voltage) Waveform Register .............................................................................................................. 49–33
FFT Accelerator (FFTA)
FFTA Features.............................................................................................................................................. 50–1
FFTA Functional Description ...................................................................................................................... 50–2
ADSP-SC58x FFTA Register List ............................................................................................................. 50–2
FFTA Definitions ..................................................................................................................................... 50–3
ADSP-SC58x FFTA Interrupt List .......................................................................................................... 50–3
ADSP-SC58x FFTA Trigger List............................................................................................................... 50–4
FFTA Block Diagram................................................................................................................................ 50–4
FFTA Programming Model.......................................................................................................................... 50–5
FFTA Use Cases........................................................................................................................................ 50–5
Single-Shot FFT ....................................................................................................................................... 50–5
Pipelined Small FFT................................................................................................................................. 50–6
Pipelined Small Interleaved FFT and IFFT Operations ........................................................................... 50–6
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference

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