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Memory transition time
The number of bus idle cycles extending the idle time cycles. These idle cycles occur in the case where a subsequent
access has a different data direction or the access is to a different bank.
Bus contention
State of the bus in which more than one device on the bus attempts to place values on the bus at the same time. For
more information, see
Avoiding Bus
ARDY signal
The SMC uses the SMC_ARDY signal to insert wait states for slower asynchronous memories. There is no upper
limit to how many wait states the SMC_ARDY signal can enter. As long as it is held, the processor waits for the
access to the asynchronous memory. Once asserted, the processor accesses the memory according to the timing dia-
grams. For more information, see
SMC Functional Description
The SMC contains memory-mapped registers that control the access characteristics for each asynchronous memory
bank. Different banks can be programmed in various modes and independently-controlled using the functional and
cycle time bit settings for each bank.
Independent bank control
The SMC provides separate sets of registers,
through
SMC_B3TIM
mode and timing characteristic of each bank independently. The control registers contain bits for enabling the
bank and bits for selecting mode of operation.
Bank select control signal control
The control registers also contain bits to control the type of bank select control signal. External FIFO devices
often do not have a separate chip select pin. As a result, for a read, the FIFOs output enable (SMC_AOE) pin
must be connected to the OR of the SMC_AMS0 and the SMC_ARE. Similarly, the write case requires an OR
between SMC_AMS0 and SMC_AWE. The SMC provides this function so that an external OR gate is not re-
quired. The appropriate AMS function can be selected for each memory bank region using the
SMC_B0CTL.SELCTRL bits.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Contention.
ARDY Input
Control.
SMC_B0CTL
(timing) and
SMC_B0ETIM
through
SMC_B3CTL
through
SMC_B3ETIM
SMC Functional Description
(control),
SMC_B0TIM
(extended timing) to control the
11–3
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