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Port x Function Enable Register
The
register bits indicate each port bit's operating mode: general purpose I/O mode or peripheral
PORT_FER
mode. After reset, all pins default to GPIO mode. Setting a bit in the
module to take ownership of the pin. The function enable bits impact output control only. Regardless of the setting
of the function enable bits, both GPIO and peripherals can still sense the pin input. After a function is enabled, it is
up to the
PORT_MUX
registers as to which peripheral takes control.
PX15 (R/W)
Port x Bit 15 Mode
PX14 (R/W)
Port x Bit 14 Mode
PX13 (R/W)
Port x Bit 13 Mode
PX12 (R/W)
Port x Bit 12 Mode
PX11 (R/W)
Port x Bit 11 Mode
PX10 (R/W)
Port x Bit 10 Mode
PX9 (R/W)
Port x Bit 9 Mode
PX8 (R/W)
Port x Bit 8 Mode
Figure 14-14: PORT_FER Register Diagram
Table 14-15: PORT_FER Register Fields
Bit No.
(Access)
15
PX15
(R/W)
14
PX14
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Port x Bit 15 Mode.
The PORT_FER.PX15 bit indicates the operating mode for port x.
Port x Bit 14 Mode.
The PORT_FER.PX14 bit indicates the operating mode for port x.
PORT_FER
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 GPIO Mode
1 Peripheral Mode
0 GPIO Mode
1 Peripheral Mode
ADSP-SC58x PORT Register Descriptions
registers enables a peripheral
1
0
0
0
PX0 (R/W)
Port x Bit 0 Mode
PX1 (R/W)
Port x Bit 1 Mode
PX2 (R/W)
Port x Bit 2 Mode
PX3 (R/W)
Port x Bit 3 Mode
PX4 (R/W)
Port x Bit 4 Mode
PX5 (R/W)
Port x Bit 5 Mode
PX6 (R/W)
Port x Bit 6 Mode
PX7 (R/W)
Port x Bit 7 Mode
17
16
0
0
14–39
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