Analog Devices ADSP-SC58 Series Hardware Reference Manual page 280

Table 7-12: SEC_CSTAT[n] Register Fields (Continued)
Bit No.
(Access)
9 ACTV
(R/NW)
8 PNDV
(R/NW)
5:4 ERRC
(R/NW)
1 ERR
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
ACT Valid.
The SEC_CSTAT[n].ACTV bit indicates (if set) that the current value in the
SEC_CACT[n]
updating the
SEC_CSTAT[n].ACTV bit is cleared when the
PND Valid.
The SEC_CSTAT[n].PNDV bit indicates (if set) that the current value in the
SEC_CPND[n]
updating the
SEC_CSTAT[n].PNDV bit is cleared when the
Error Cause.
The SEC_CSTAT[n].ERRC bits are updated on assertion of the
SEC_CSTAT[n].ERR bit to indicate the SCI error type. SEC_CSTAT[n].ERRC
is only updated on the assertion of SEC_CSTAT[n].ERR. Subsequent errors while
SEC_CSTAT[n].ERR is asserted do not update SEC_CSTAT[n].ERRC.
Error.
The SEC_CSTAT[n].ERR bit indicates that an error has occurred in the SCI.
When SEC_CSTAT[n].ERR is set, the SCI updates the SEC_CSTAT[n].ERRC
field to the value of the corresponding error cause.
Description/Enumeration
register is valid. The SCI sets the SEC_CSTAT[n].ACTV bit when
SEC_CACT[n] registers with a new value. The
0 Invalid
1 Valid
register is valid. The SCI sets the SEC_CSTAT[n].PNDV bit when
register with a new value. The
SEC_CPND[n]
0 Invalid
1 Valid
0 Reserved
1 Acknowledge Error. SCI has received an acknowledge
without a pending, unacknowledged interrupt present.
2 Reserved
3 Reserved
0 No Error
1 Error Occurred
ADSP-SC58x SEC Register Descriptions
register is written.
SEC_CSID[n]
SEC_CSID[n] register is written.
7–35