Table of Contents
Advertisement
Figure 11-7: Asynchronous Flash Read with Pre-Setup and Pre-Access Cycles
In this case, the target SMC bank has been programmed with:
• Pre-setup time = 1 cycle
• Read setup time = 2 cycles
• Pre-access time = 1 cycle
• Read access time = 5 cycles
• Read hold time = 2 cycles
The read bus cycle is almost identical to the asynchronous SRAM read bus cycle. The only difference is the behavior
of the SMC_AOE signal which the SMC uses as the flash address valid SMC_NORDV signal. The flash address valid
SMC_NORDV signal asserts at the start of the setup cycle and deasserts at the end of the setup cycle.
The pre-access cycle inserts a one-cycle gap between the deassertion of the flash address valid SMC_NORDV signal
and the assertion of the flash read strobe NOR_OE at the start of read access. The SMC also uses asynchronous flash
reads with SMC_ARDY enabled for flash devices which use SMC_NORWT in asynchronous mode. In this case, the
read bus cycle operation is identical to the asynchronous SRAM with SMC_ARDY enabled except for the
SMC_AOE/SMC_NORDV signal behavior.
The 32-bit Asynchronous Flash Read figure shows a 32-bit read access to a flash device in asynchronous mode which
is split into two 16-bit external memory accesses. For this bank, read setup and read hold are programmed as two
cycles whereas the read access time is five cycles. The flash device chip select signal (NOR_CE) remains asserted for
the entire duration of both read accesses. NOR_CE is deasserted at the end of the hold period of the second read
access. The SMC asserts the SMC_NORDV signal during the setup phase of both read accesses. Read data is latched
at the end of the read access period.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Pre-Setup
Pre-Access
1 Cycle
1 Cycle
Setup
2 Cycles
CLKOUT
NOR_An
A0
NOR_CE
NOR_ADV
NOR_OE
NOR_DQ15-0
SMC Programmable Timing Characteristics
Read Data
Latched Here
Read Access
Hold
5 Cycles
2 Cycles
D
11–13
Advertisement
Table of Contents
