Analog Devices ADSP-SC58 Series Hardware Reference Manual page 689

shows how FIFO slots influence the acknowledge signal generation. The grayed sections show received data. The
white sections show empty locations where the decision to pull LP_ACK high is taken.
Figure 15-8: LACK Generation Based on Receive FIFO Status
The link port uses a 4-deep receive FIFO only under a worst case situation, as mentioned. In all other
NOTE:
cases, respond as if the FIFO has only a 3-deep stage. The LP_ACK signal is pulled high before the last
stage of the FIFO.
The link port has memory-mapped buffers for both receive and transmit operations. A JTAG-based emulator can
read the FIFO which can cause unexpected problems in data transfers. This activity can only happen during an em-
ulation event (typically hitting a breakpoint or single-stepping). The emulator issues core reads through JTAG. To
work around this issue, see the tools documentation for more information.
Handshake for Link Port Enable Process
In a link port-based system, the transmitter and the receiver can be enabled at different times. Use external pull-
downs for the LP_CLK and LP_ACK signals.
If the receiver is enabled before the transmitter, the external pull-down holds the LP_CLK signal of the transmitter
low. The receiver is held off. The receiver can wait for a rising edge on the LP_CLK signal to assert its receive service
request interrupt. This rising edge occurs only when transmitter starts driving the first data on to the bus, after the
application enables it.
If the transmitter is enabled before the receiver, the external pull-down holds the LP_ACK signal of the receiver low.
Transmission is held off. Refer to the Enable the Transmitter Before the Receiver figure. The transmitter can wait for
a rising edge on the LP_ACK signal to assert its transmit service request interrupt. This rising edge is asserted as
soon as the receiver is enabled after the hardware drives the LP_ACK high.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
32-BIT
32-BIT
8-BIT 24-BIT
32-BIT
Architectural Concepts
15–9