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Functional Description
• Support for single-precision and double-precision floating-point formats
• Support for conversion between half-precision and single-precision
• Support for Fused Multiply Accumulate (FMA) operations
• Normalized and de-normalized data are all handled in hardware
• Trap-less operation enabling fast execution
NeON
The Cortex-A5 NEON MPE extends the Cortex-A5 functionality to provide support for the ARM v7 Advanced
SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction sets. The Cortex-A5 NEON MPE supports all address-
ing modes and data-processing operations described in the ARM Architecture Reference Manual.
The Cortex-A5 NEON MPE features are:
• SIMD and scalar single-precision floating-point computation
• scalar double-precision floating-point computation
• SIMD and scalar half-precision floating-point conversion
• SIMD 8, 16, 32, and 64-bit signed and unsigned integer computation
• 8 or 16-bit polynomial computation for single-bit coefficients
• structured data load capabilities
• Large, shared register file, addressable as:
• 32 32-bit S (single) registers
• 32 64-bit D (double) registers
• 16 128-bit Q (quad) registers
• The operations include:
• Addition and subtraction
• Multiplication with optional accumulation
• Maximum or minimum value driven lane selection operations
• Inverse square-root approximation
• Comprehensive data-structure load instructions, including register-bank-resident table lookup
See the ARM Architecture Reference Manual for details of the extension register set.
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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