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Clock Rate Register
The
register divides the system clock ( SCLK0_0) down to the bit clock.
UART_CLK
Figure 17-11: UART_CLK Register Diagram
Table 17-10: UART_CLK Register Fields
Bit No.
(Access)
31
EDBO
(R/W)
15:0
DIV
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
1
1
1
DIV (R/W)
Divisor
31
30
29
0
0
0
EDBO (R/W)
Enable Divide By One
Bit Name
Enable Divide By One.
The UART_CLK.EDBO bit enables the bypassing of the divide-by-16 prescaler in bit
clock generation. This functionality improves bit rate granularity, especially at high bit
rates. Do not set this bit in IrDA mode.
Divisor.
The UART_CLK.DIV provides the divisor for the UART's clock bit rate calculation.
The bit rate is defined by:
Bit Rate = SCLK0_0 / (16
12
11
10
9
8
7
6
5
1
1
1
1
1
1
1
1
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 Bit clock prescaler = 16
1 Bit clock prescaler = 1
(1-EDBo)
x UART_CLK.DIV)
ADSP-SC58x UART Register Descriptions
4
3
2
1
0
1
1
1
1
1
20
19
18
17
16
0
0
0
0
0
17–25
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