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ADSP-SC58x DMC Register Descriptions
Shadow MR1 Register (DDR3)
The
register is a mirror of the DDR3 SDRAM Mode register 1. This register is used only when the
DMC_MR1
DMC is operating in DDR3 mode. A write to this register triggers an extended "mode register 1 set" command on
the memory interface provided the corresponding mask bit is set in the mask register. Else, only the mirror register is
updated.
QOFF (R/W)
Output Buffer Enable
TDQS (R/W)
Termination Data Strobe
RTT2 (R/W)
Rtt_nom
RTT1 (R/W)
Rtt_nom
DIC1 (R/W)
Output Driver Impedance Control
Figure 10-13: DMC_MR1 Register Diagram
Table 10-22: DMC_MR1 Register Fields
Bit No.
(Access)
12
QOFF
(R/W)
11
TDQS
(R/W)
10–46
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Output Buffer Enable.
The DMC_MR1.QOFF bit enables the SDRAM output pins. For more information
about this operation, see the data sheet for the SDRAM being used in your system.
Termination Data Strobe.
The DMC_MR1.TDQS bit provides additional termination resistance outputs that may
be useful in some system configurations. The DMC_MR1.TDQS bit is not supported
in x4 or x16 configurations. When enabled via the mode register, the same termination
resistance function is applied to the TDQS/TDQS# pins that is applied to the DQS/
DQS# pins.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
0 Output buffer enabled
1 Output buffer disabled
0 Enable
1 Disable
DLLEN (R/W)
DLL Enable
DIC0 (R/W)
Output Driver Impedance control
RTT0 (R/W)
Rtt_nom
AL (R/W)
Additive Latency
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