Analog Devices ADSP-SC58 Series Hardware Reference Manual page 61

Segmented-Buffer VC0 Completion Receive Queue Control Register ................................................. 29–336
Segmented-Buffer VC0 Non-Posted Receive Queue Control Register ................................................. 29–337
Segmented-Buffer VC0 Posted Receive Queue Control Register .......................................................... 29–338
Virtual Channel Transmit Arbitration Register 1 ................................................................................. 29–340
Virtual Channel Transmit Arbitration Register 2 ................................................................................. 29–342
Vendor Specific DLLP Register ............................................................................................................ 29–344
Two-Wire Interface (TWI)
TWI Features............................................................................................................................................... 30–1
TWI Functional Description ....................................................................................................................... 30–2
ADSP-SC58x TWI Register List .............................................................................................................. 30–2
ADSP-SC58x TWI Interrupt List ........................................................................................................... 30–2
TWI Block Diagram................................................................................................................................. 30–3
External Interface .................................................................................................................................. 30–3
Serial Clock Signal (SCL)................................................................................................................... 30–3
Serial Data Signal (SDA).................................................................................................................... 30–4
Internal Interface................................................................................................................................... 30–4
TWI Architectural Concepts .................................................................................................................... 30–5
TWI Protocol........................................................................................................................................ 30–5
Clock Generation and Synchronization ................................................................................................. 30–6
Bus Arbitration ..................................................................................................................................... 30–6
Start and Stop Conditions ..................................................................................................................... 30–7
General Call Support............................................................................................................................. 30–7
Fast Mode ............................................................................................................................................. 30–8
TWI Operating Modes ................................................................................................................................ 30–8
Repeated Start .......................................................................................................................................... 30–8
Transmit Receive Repeated Start............................................................................................................... 30–8
Receive Transmit Repeated Start............................................................................................................... 30–9
Clock Stretching ....................................................................................................................................... 30–9
Clock Stretching During FIFO Underflow .......................................................................................... 30–10
Clock Stretching During FIFO Overflow ............................................................................................ 30–10
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference lxi