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In pulse mode 10, a PWM channel is in full off modulation if the high-side output of that channel is deasserted.
The output is deasserted for the whole duration of the first half period of the PWM timer that the channel is refer-
encing. In the second half-period, it is deasserted anyway. The conditions for full off modulation are:
• PWM_xH0 DT < PWM_TMy/2 for pulse mode 10
• PWM_xH1 + DT < PWM_xH0 DT for pulse mode 10
In pulse mode 11, a PWM channel is in full off modulation if the high-side output of that channel is deasserted.
The output is deasserted for the whole duration of the second half period of the PWM timer that the channel is
referencing. In the first half of the period, it is deasserted anyway. The conditions for full off modulation are:
• PWM_xH0 + DT > PWM_TMy/2 for pulse mode 11
• PWM_xH1 DT > PWM_xH0 + DT for pulse mode 11
Normal Modulation
All other cases of modulation fall under this category.
Emergency Dead-Time Delays
Sometimes, during modulation transition, it is necessary to insert more emergency dead-time delays to prevent po-
tential shoot through conditions in the inverter. (For example, when the PWM transitions into or out of full on or
full off modulation.) Disabling and enabling usage (related to the PWM_ACTL.DISHI and PWM_ACTL.DISLO
bits) also can potentially cause outputs to violate shoot-through condition criteria. Another case is when large values
vary the phase delay of a PWM timer. These transitions are detected automatically. If appropriate for safety, an
emergency dead-time is inserted to prevent shoot through conditions.
There is another atypical case for the insertion of the additional emergency dead time. It occurs when both PWM
signals do not toggle within a dead time of each other. In this case, insert more emergency dead time into one of the
PWM signals of a given pair during these transitions. The dead-time delay is inserted into the PWM signal that is
toggling into the on-state. In effect, an amount (2 × DT × t
the turn-on of this signal. After this delay, the PWM signal is allowed to turn-on provided the desired output is still
scheduled to be in the on-state after the emergency dead-time delay.
The Over Modulation Transition Example figure illustrates two examples of such a transition. In the figure,
PWM_ACTL.PULSEMODEHI is kept at 1. The PWM_AH signal has been in full on modulation for some time and,
during the current period, its pulse mode is changed to 10, keeping the full on condition. At the half-period boun-
dary, PWM_AH is forced to transition to a deasserted state because pulse mode is 10. An emergency dead-time is
inserted on the low-side output.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
) from the rising edge of the opposite output delays
CK
Channel Timing Control Unit
19–23
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