Table of Contents
Advertisement
EPPI Programming Model
Table 18-45: 16-bit Split Transmit Mode with SPLTWRD = 1, SUBSPLTODD = 1, and SWAPEN = 0 (Continued)
DMACFG = 1
PRIMARY DMA DATA
(32 bits)
Y
Y
Y
Y
7
6
5
4
EPPI Programming Concepts
This section provides information on SMPTE programming.
SMPTE Modes Programming
The programming model of SMPTE modes is similar to ITU Modes. All programming modes pertaining to ITU
modes like XFRTYPE, FSCFG, FLDSEL, and BLANKGEN hold true for SMPTE modes as well. The only differ-
ence is that since ITU modes use Y-Cr/Cb interleaved data and SMPTE use parallel Y-Cr/Cb data, SPLTWRD
could be set while operating in SMPTE modes. The Programming Modes for SMPTE Formats table describes the
programming modes for different SMPTE formats.
Table 18-46: Programming Modes for SMPTE Formats
SMPTE Format
SMPTE Channel
Width
8
296M
8
ADSP-SC58x EPPI Register Descriptions
Enhanced Parallel Peripheral Interface (EPPI) contains the following registers.
18–52
SECONDARY DMA
Pin Data (16 bits)
DATA (32 bits)
U
U
U
U
U
3
2
1
0
V
V
V
V
V
7
6
5
4
U
U
U
U
U
7
6
5
4
V
U
V
U
EPPI Input Bit Width
16
Cr/Cb - [15:8]
Y - [7:0]
16
Cr/Cb - [15:8]
Y - [7:0]
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMACFG = 0
DMA0 DATA (32 bits)
Y
Y
0
1
3
Y
U
1
2
3
Y
Y
1
3
7
Y
2
4
Y
2
5
Y
3
6
Y
3
7
EPPI Mode
DLEN = 16 bits
SPLTWRD = 1
DLEN = 16 bits
SPLTWRD = 1
Pin Data (16 bits)
Y
Y
Y
U
2
1
0
0
U
U
U
V
2
1
0
1
Y
Y
Y
U
6
5
4
1
V
2
U
2
V
3
U
3
Remarks
SIGNEXT not supported
SIGNEXT not supported
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Advertisement
Table of Contents
